SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 110

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 115. Data Port register (address 0220h) bit description
Table 116. Buffer Length register (address 021Ch) bit description
SAF1761_1
Product data sheet
Bit
15 to 0
Bit
15 to 0 DATACOUNT
Symbol
[15:0]
Symbol
DATAPORT
[15:0]
10.4.4 Buffer Length register
10.4.5 DcBufferStatus register
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit description is given in
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see
required. After a bus reset, the Buffer Length register is made zero.
IN endpoint: When the data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring data
that is not a multiple of MaxPacketSize. The following two examples demonstrate the
significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be filled. This is because the
transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just
before the microcontroller writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use the VENDP bit in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
This register is accessed using an index. The endpoint index must first be set before
accessing this register for the corresponding endpoint. It reflects the status of the endpoint
FIFO.
Remark: This register is not applicable to the control endpoint.
Access Value
R/W
Access
R/W
Table 117
0000h
Value
0000 0000h
shows the bit allocation of the DcBufferStatus register.
Description
Data Count: Determines the current packet size of the indexed endpoint
FIFO.
Rev. 01 — 18 November 2009
Description
Data Port: A 500 ns delay starting from the reception of the endpoint
interrupt may be required for the first read from the data port.
Table
Table
116.
120). A smaller value can be written when
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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