SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 120

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 139. DMA Burst Counter register (address 0264h) bit allocation
[1]
Table 140. DMA Burst Counter register (address 0264h) bit description
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
15 to 13
12 to 0
The reserved bits should always be written with the reset value.
Symbol
-
BURST
COUNTER[12:0]
10.5.9 DMA Burst Counter register
10.6.1 DcInterrupt register
10.6 General registers
R/W
R/W
15
0
0
7
0
0
The bit allocation of the register is given in
The DcInterrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the DcInterrupt register content is non-zero, the INT output
will be asserted. On detecting the interrupt, the external microprocessor must read the
DcInterrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.
reserved
Description
reserved
Burst Counter: This register defines the burst length. The counter must be programmed to
be a multiple of two in 16-bit mode and four in 32-bit mode.
The value of the burst counter must be programmed so that the buffer counter is a factor of
the burst counter. In 16-bit mode, DREQ will drop at every DMA read or write cycle when the
burst counter equals 2. In 32-bit mode, DREQ will drop at every DMA read or write cycle
when the burst counter equals 4.
R/W
R/W
14
0
0
6
0
0
[1]
R/W
R/W
13
0
0
5
0
0
Rev. 01 — 18 November 2009
BURSTCOUNTER[7:0]
R/W
R/W
12
0
0
4
0
0
Table
R/W
R/W
11
0
0
3
0
0
BURSTCOUNTER[12:8]
139.
R/W
R/W
10
0
0
2
1
1
Hi-Speed USB OTG controller
R/W
R/W
9
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
Table
141.
120 of 166
R/W
R/W
8
0
0
0
0
0