SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 19

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
7.3.1 PIO mode access, memory read cycle
7.3 Accessing the SAF1761 host controller memory: PIO and DMA
Table 4.
Both the CPU interface logic and the USB host controller require access to the internal
SAF1761 RAM at the same time. The internal arbiter controls these accesses to the
internal memory, organized internally on a 64-bit data bus width, allowing a maximum
bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the
CPU interface and the internal USB host controller.
The CPU interface of the SAF1761 can be configured for a 16-bit or 32-bit data bus width.
When the SAF1761 is configured for a 16-bit data bus width, the upper unused 16 data
lines must be pulled up to V
together to a single 10 k pull-up resistor. The 16-bit or 32-bit data bus width
configuration is done by programming bit 8 of the HW Mode Control register. This will
determine the register and memory access types in both PIO and DMA modes to all
internal blocks: host controller, peripheral controller and OTG controller. All accesses must
be word-aligned for 16-bit mode and double word aligned for 32-bit mode, where one
word = 16 bits. When accessing the host controller registers in 16-bit mode, the register
access must always be completed using two subsequent accesses. In the case of a DMA
transfer, the 16-bit or 32-bit data bus width configuration will determine the number of
bursts that will complete a certain transfer length.
In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA
mode, the data validation is performed by DACK, instead of CS_N, together with the
WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the
SAF1761 DMA is enabled.
The following method has been implemented to reduce the read access timing in the case
of a memory read:
Memory map
ISO
INT
ATL
Payload
•
•
The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an
appropriate value is written to this register.
Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to pre-fetch data for the memory read of that bank.
For every subsequent read operation executed at a contiguous address, the address
pointer corresponding to that bank is automatically incremented to pre-fetch the next
data to be sent to the CPU.
Memory read accesses for multiple banks can be interleaved. The FIFO block
handles the multiplexing of appropriate data to the CPU.
Memory address
Rev. 01 — 18 November 2009
CC(I/O)
CPU address
0400h to 07FFh
0800h to 0BFFh
0C00h to 0FFFh
1000h to FFFFh
. This can be achieved by connecting DATA[31:16] lines
Hi-Speed USB OTG controller
Memory address
0000h to 007Fh
0080h to 00FFh
0100h to 017Fh
0180h to 1FFFh
SAF1761
© NXP B.V. 2009. All rights reserved.
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