SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 114

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 123. Control bits for GDMA read or write (opcode = 00h/01h)
Table 124. DMA Command register (address 0230h) bit allocation
Table 125. DMA Command register (address 0230h) bit description
Table 126. DMA commands
SAF1761_1
Product data sheet
Control bits
Mode register
DMACLKON
DcDMAConfiguration register
MODE[1:0]
WIDTH
DIS_XFER_CNT
DMA Hardware register
DMA_XFER_EN
DACK_POL,
DREQ_POL
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 0
Code
00h
01h
02h to 0Dh
0Eh
Symbol
DMA_CMD[7:0] DMA command code; see
Name
GDMA Read
GDMA Write
-
Validate Buffer
10.5.2 DMA Command register
W
7
1
1
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-state.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activities on the DMA controller. The register is write-only:
reading it will return FFh.
Remark: The DMA bus will be in 3-state until a DMA command is executed.
Description
Set DMACLKON to logic 1
Determines the active read or write data strobe signals
Selects the DMA bus width: 16-bit or 32-bit
Disables the use of the DMA Transfer Counter
Enables DMA transfer
Select the polarity of the DMA handshake signals
Description
Description
Generic DMA IN token transfer: Data is transferred from the external DMA bus to the
internal buffer.
Generic DMA OUT token transfer: Data is transferred from the internal buffer to the
external DMA bus.
reserved
Validate Buffer (for debugging only): Request from the microcontroller to validate the
endpoint buffer, following a DMA-to-USB data transfer.
W
6
1
1
Rev. 01 — 18 November 2009
W
5
1
1
Table
DMA_CMD[7:0]
W
4
1
1
126.
W
3
1
1
Hi-Speed USB OTG controller
W
2
1
1
Reference
Table 101
Table 130
Table 132
W
SAF1761
1
1
1
Table
© NXP B.V. 2009. All rights reserved.
124) that
114 of 166
W
0
1
1