SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 122

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit description
Table 143. DcChipID - Device Controller Chip Identifier register (address 0270h) bit description
Table 144. Frame Number register (address 0274h) bit allocation
SAF1761_1
Product data sheet
Bit
9
8
7
6
5
4
3
2
1
0
Bit
31 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Symbol
-
EP0SETUP
VBUS
DMA
HS_STAT
RESUME
SUSP
PSOF
SOF
BRESET
Symbol
CHIPID[31:0]
10.6.2 DcChipID register
10.6.3 Frame Number register
15
R
R
0
0
7
0
0
reserved
This read-only register contains the chip identification and hardware version numbers.
The firmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in
This read-only register contains the frame number of the last successfully received
Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in
Table
Access
R
Description
reserved
logic 1 indicates that a SETUP token was received on endpoint 0
Logic 1 indicates a transition from LOW to HIGH on V
When implementing a pure host or peripheral, the OTG_DISABLE bit in the OTG Control
register (374h) must be set to logic 1 so that the VBUS bit is updated with the correct value.
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason register.
High-Speed Status: Logic 1 indicates a change from full-speed to high-speed mode (HS
connection). This bit is not set when the system goes into the full-speed suspend.
Resume status: Logic 1 indicates that a status change from suspend to resume (active) was
detected.
Suspend status: Logic 1 indicates that a status change from active to suspend was detected
on the bus.
Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or SOF was received. Pseudo
SOF is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 s
period) that is not synchronized to the USB bus SOF or SOF.
SOF interrupt: Logic 1 indicates that a SOF or SOF was received.
Bus Reset: Logic 1 indicates that a USB bus reset was detected.
144.
14
R
R
0
0
6
0
0
Value
0001 1582h Chip ID: This registers represents the hardware version number
13
Rev. 01 — 18 November 2009
R
R
0
0
5
0
0
Description
(0001h) and the chip ID (1582h) for the peripheral controller.
MICROSOF[2:0]
12
R
R
0
0
4
0
0
SOFR[7:0]
11
R
R
0
0
3
0
0
BUS
.
10
Hi-Speed USB OTG controller
R
R
0
0
2
0
0
Table
SOFR[10:8]
…continued
143.
R
R
SAF1761
9
0
0
1
0
0
© NXP B.V. 2009. All rights reserved.
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R
R
8
0
0
0
0
0