SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 98

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
10. Peripheral controller
SAF1761_1
Product data sheet
10.1.1.1 DMA for the IN endpoint
10.1.1.2 DMA for the OUT endpoint
10.1.1.3 DMA initialization
10.1.1 Direct Memory Access (DMA)
10.1 Introduction
The USB protocol and data transfer operations of the peripheral controller are executed
using external firmware. The external microcontroller or microprocessor can access the
peripheral controller-specific registers through the local bus interface. The transfer of data
between a microprocessor and the peripheral controller can be done in PIO mode or
programmed DMA mode.
The DMA controller of the SAF1761 is used to transfer data between the system memory
and endpoints buffers. It is a slave DMA controller that requires an external DMA master
to control the transfer.
When the internal DMA is enabled and at least one buffer is free, the DC_DREQ line is
asserted. The external DMA controller then starts negotiating for control of the bus. As
soon as it has access, it asserts the DC_DACK line and starts writing data. The burst
length is programmable. When the number of bytes equal to the burst length has been
written, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the
DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When the buffer is full, the DC_DREQ line is de-asserted and the buffer is validated,
which means that it is sent to the host at the next IN token. When the DMA transfer is
terminated, the buffer is also validated, even if it is not full.
When the internal DMA is enabled and at least one buffer is full, the DC_DREQ line is
asserted. The external DMA controller then starts negotiating for control of the bus. As
soon as it has access, it asserts the DC_DACK line and starts reading data. The burst
length is programmable. When the number of bytes equal to the burst length has been
read, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the
DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When all the data is read, the DC_DREQ line is de-asserted and the buffer is
cleared. This means that it can be overwritten when a new packet arrives.
To reduce the power consumption, a controllable clock that drives DMA controller circuits
is turned off, by default. If the DMA functionality is required by an application, DMACLKON
(bit 9) of the Mode register (address: 020Ch) must be enabled during initialization of the
peripheral controller. If DMA is not required by the application, DMACLKON can be
permanently disabled to save current. The burst counter, DMA bus width, and the polarity
of DC_DREQ and DC_DACK must accordingly be set.
The SAF1761 supports only counter mode DMA transfer. To enable counter mode, ensure
that DIS_XFER_CNT in the DcDMAConfiguration register (address: 0238h) is set to zero.
Before starting the DMA transfer, preset the interrupt enable bit IEDMA in the Interrupt
Enable register (address: 0214h) and the DMA Interrupt Enable register (address: 0254h).
The SAF1761 supports two interrupt trigger modes: level and edge. The pulse width,
which in edge mode, is determined by setting the Interrupt Pulse Width register (address:
Rev. 01 — 18 November 2009
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
98 of 166