PEF24901HV22XP Lantiq, PEF24901HV22XP Datasheet - Page 101

• Manufacturer Part Number: PEF24901HV22XP
• Manufacturer: Lantiq

Specifications of PEF24901HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

•
Table 24
DCL Data delay clock
Pin PUP = ’0’
Pin PUP = ’1’
FSC Data delay frame
Notes:
7.4.3
The AC characteristics of the AFE-interface pins are optimized to fit to AFE Version 2.1
if the following loads are not exceeded.
•
Table 25
Pin
CL15
SDR
PDM0 3
SDX
Data Sheet
Parameter
1)
either FSC (
DCL) shall be the reference.
The point of time at which the output data will be valid is referred to the rising edges of
Interface to the Analog Front End
Signal Driving Device
AFE
AFE
AFE
DFE-T
IOM
Interface Signals of AFE and DFE-T
t
®
dDF
-2 Dynamic Output Characteristics
) or DCL (
1)
1)
Symbol
t
t
t
dDC
dDC
dDF
t
dDC
). The rising edge of the signal appearing last (normally
min. typ.
Limit Values
102
Max. Capacitive Load
Max. Connection Resistance
50 pF; 2
20 pF; 2
20 pF; 2
20 pF; 2
max.
100
40
20
Unit Test Condition
ns
ns
ns
Electrical Characteristics
C
Charged with 5 V
C
Charged with 3.3 V
C
L
L
L
= 150 pF,
= 100 pF,
= 150 pF
PEF 24901
2002-09-30
DFE-T