PEF24901HV22XP Lantiq, PEF24901HV22XP Datasheet - Page 29

• Manufacturer Part Number: PEF24901HV22XP
• Manufacturer: Lantiq

Specifications of PEF24901HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Table 1
Pin No.
52
61
49
53
JTAG Boundary Scan
64
1
2
3
63
Power Supply Pins
6, 22, 38, 54
9, 25, 41, 57
1)
Data Sheet
In case that JTAG is reset via TRST = 0, pin TCK shall be pulled to either power or ground, e.g. with a pull-
down of 47 k .
Pin Definitions and Functions (cont’d)
Symbol
CLS2
CLS3
N.C.
N.C.
TCK
TMS
TDI
TDO
TRST
VDD
VSS
Input (I)
Output (O)
O
O
I
I
I
I
(PU)
I
(PU)
O
I
(PU)
Test Clock
Test Data Output
Function
Clock of 1 ms period to indicate the received
frame of Port 2
can be used for monitoring and test purposes
Clock of 1 ms period to indicate the received
frame of Port 3
can be used for monitoring and test purposes
No function
May be clamped to ground for compatibility to
former versions.
No function
May be clamped to VDD for compatibility to
former versions.
Test Mode Select
Test Data Input
JTAG Boundary Scan Disable
resets the TAP controller state machine
(asynchronous reset), active low. Clamp
TRST to GND if the Boundary Scan logic is not
used
’1’= reset inactive
’0’= reset active
3.3 V 0.3 V supply voltage
0 V ground
30
1)
Pin Descriptions
PEF 24901
2002-09-30
DFE-T