PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet
PEB2096HV31XT
Specifications of PEB2096HV31XT
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PEB2096HV31XT Summary of contents
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ICs for Communications Octal Transceiver for U OCTAT-P PEB 2096 Version 2.1 Data Sheet 04.99 Interfaces ...
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PEB 2096 Revision History: Previous Releases: Page Page Subjects (major changes since last revision) (in (in current previous Version) Version Pin Configuration (correction pin 17 and 18 Data rate on IOM-2 interface 8192 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.4 Test Registers – (Read/Write ...
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Overview The new Infineon Technologies generation of highly integrated ISDN circuits enables design engineers to decrease board size and thus PBX size and its production costs. Figure 1-1 shows an example of a PBX for 16 ISDN and 16 ...
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Enhanced Line Card Controller (PEB 20550), one SIDEC, 4-channel signaling controller (LAPD), multiple IOM-2 and PCM interfaces, one MIPS DSP with on-chip emulation and a Mailbox, one PCM-DSP interface for fast DSP access, one UART, Interrupt Controller, ...
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Octal Transceiver for U OCTAT-P Version 2.1 1.1 Features • Eight full duplex 2B+D U each equipped with the following functions: –Conversion from/to binary to/from pseudo-ternary code –Receive timing recovery –Activation/deactivation procedures, triggered by primitives received over the IOM interface ...
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Logic Symbol • Figure 1-2 Logic Symbol Data Sheet 1-4 PEB 2096 Overview 04.99 ...
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Pin Configuration (top view) • CLK2 Figure 1-3 Pin Configuration Data Sheet P-MQFP- CLK1 RST 38 IDS DCL 42 FSC ...
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Pin Definitions and Functions Pin No. Symbol Input ( 12, 22, 28 19, SS 25, 31, 37 33, 32 LI0a,b 30, 29 LI1a,b 27, 26 LI2a,b 24, 23 LI3a ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) 18 SSYNC I 17 MODE Data Sheet Function Output (O) Superframe synchronization I This pin selects the initial values of the General Configuration Register and in the Configuration Register ...
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Block Diagram • Figure 1-4 Block Diagram Data Sheet 1-8 PEB 2096 Overview 04.99 ...
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Functional Description The PEB 2096, OCTAT-P, performs the layer-1 functions of the ISDN basic access for eight U interfaces at the LT side of the PBX. PN 2.1 Device Architecture The OCTAT-P contains the following functional blocks: Refer to ...
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LT TE/ Figure 2-1 U Interface Frame Structure (= U P0 Within a burst, the data rate is 384 kbit/s. The 38-bit frame structure is as shown in Figure 2-1. The framing bit ...
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S-channel bit is transmitted once in each direction in every fourth burst repetition period. Hence the duplex S channel has a data rate of 1 kbit/s. It conveys test loop control information from the LT to the TE/PT and reports ...
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IOM -2 System Interface ® The PEB 2096, OCTAT-P, is equipped with a digital ISDN Oriented Modular (IOM-2) interface, for communication with upper layer functions, such as IDEC (PEB 2075), EPIC (PEB 2055) and ELIC (PEB 20550). EPIC and ...
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FSC DCL R IOM CH0 CH1 DU R IOM CH0 CH1 DD B1 Figure 2-4 Multiplexed Frame Structure of the IOM 2.048 Mbit/s Data Rate Each IOM channel consists of a total of 32 bits, or four octets: B1 ...
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In order to allow the use of the eight channels also with a maximum clock rate of 2,048 kHz provided by the system, the OCTAT-P can also run the IOM interface with only half the nominal DCL clock rate, i.e. ...
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Data Rates on IOM-2 Interface The OCTAT-P supports the following types of IOM-2 interfaces: • Table 1 Mode of IOM-2 Interface Nominal bit rate of data (DD and DU) Nominal frequency of DCL (2 x data rate) Selectable frequency of ...
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Boundary Scan Test The following OCTAT-P pins are included in the boundary scan: CLK2, CLK1, RST, IDS, DU, DD, DCL, FSC, MODE, SSYNC, XTAL1. Three additional user specific instruction codes control the transmission of continuous pulses at the line ...
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TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE St. 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. The TAP controller supports 8 ...
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IDCODE The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). The LSB is fixed to “1”. Code for the Version 2.1 ...
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User Specific Instructions Three different user specific pulse types are selectable, Figure 2-5. An oscillator with a 15.36 MHz clock or an external clock is necessary for 192 kHz test pulse generation; according to the instruction code 9 • Figure ...
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Individual Functions 2.3.1 Transceiver, Analog Connections The receiver input stages consist of an amplifier/equalizer, followed by a peak detector adaptive controlling the thresholds of the comparators and a digital oversampling unit. • Figure 2-6 Transceiver Functional Blocks External to ...
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Figure 2-7 Transceiver with a 2:1 Transformer • Figure 2-8 Transceiver with a 1.25:1 Transformer Data Sheet Functional Description 2-13 PEB 2096 04.99 ...
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The PEB 2096, OCTAT-P, covers the electrical requirements of the U loop lengths depending on the used transformer and the cable quality the equalizer is enabled (EQUDIS in Configuration Register for U Transformer 2 the equalizer ...
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Receive Signal Oversampling In order to additionally reduce the bit error rate in severe conditions, the OCTAT-P performs oversampling of the received signal and uses majority decision logic. As illustrated in Figure 2-9, each received bit is sampled 6 ...
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Activation / Deactivation An incorporated finite state machine controls the activation and deactivation procedures and communicates with the layer-2 unit via the IOM-2 C/I channel. Each of the eight C/ I channels is allocated to its corresponding line interface. ...
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Operational Description 3.1 General All procedures required for data transmission over the U These comprise the U PN deactivation procedure, and timing requirements such as bit rate and jitter. The internal finite state machine of the PEB 2096, OCTAT-P, ...
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The sensing is done within 2 consecutive IOM frames at bit position 15 (last bit of B2 channel). The pin DU is always push-pull if the MODE pin is connected to 3.5 Transmit Delay on U The OCTAT-P causes ...
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U Multiframe Synchronization PN There are two possibilities how to synchronize the U with SSYNC. 3.6.1 Synchronization with a Short FSC The short FSC pulse has a width of one DCL clock (in normal use the FSC is at ...
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Synchronization using SSYNC (for DECT) A zero pulse on the SSYNC input forces the OCTAT-P to start a multiframe with a code violation in the next M-bit. Refer to Figure 3-3. • Figure 3-3 Synchronization with SSYNC While using ...
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D-Channel Handling Decentralized D-Channel processing can be realized by the use of only one multiplexed HDLC-Controller, which is integrated with a D-channel Arbiter in the ELIC, PEB 20550. Typically the D-channel load has a very bursty characteristic. Taking this ...
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The control channel is unidirectional and forwards the status information of the corresponding D-channel (blocked or available) towards the subscriber terminal. Different existing channel structures are used to implement the control channel between the HDLC-controllers on the line card and ...
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Figure 3-5 Control Channel Implementation with OCTAT Card Transceiver and S-Adapter. Data Sheet Operational Description -P (PEB 2096) as Line ® 3-7 PEB 2096 04.99 ...
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IOM -2 Interface Monitor Channel ® The monitor channel is used to convey message oriented information. This means that an information in the monitor channel is transferred once, and the receiver stores that message. There is a defined handshake ...
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Figure 3-6 Monitor Channel Handling: P Data Sheet Operational Description ELIC OCTAT-P 3-9 PEB 2096 04.99 ...
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A detailed description of the hand-shake procedure using MX and MR bits is shown on Figure 3-7. • Figure 3-7 Monitor Channel Handling: Hand-shake by the Use of MX and MR Bits Data Sheet Operational Description 3-10 PEB 2096 04.99 ...
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Command / Indicate Channel The C/I channel is used for communication between the OCTAT-P and a layer-2 device (or ELIC), to control and monitor layer-1 functions. The layer-2 device monitors the layer-1 indication continuously and indicates a change if ...
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Table 3 Indications Indication (upstream) Timing required (to activate IOM-2) Resynchronization (loss of framing) Activate request U only activation indication Activate indication Deactivate indication In PBX applications with decentral D-channel handling, all D-channels can be handled by a D-channel arbiter ...
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Activation and Deactivation, State Machine The activation and deactivation implemented in the PEB 2096, OCTAT-P, agree with the U interface as implemented in the PEB 2095, IBC. P0 3.10.1 States Description OCTAT-P state machine enters two different kind of ...
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ARx i1 i1 RSY ARx,Al DR Resynchron Unconditional Transitions Initiated by Commands: RES, TM1, TM2 External Pins: RST ARx = AR, AR2, ARL Figure 3-8 OCTAT-P State Diagram Data Sheet TM1 TIM TM2 Test ...
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Unconditional States Reset This state is entered unconditionally after a high appears on the RST pin or after the receipt of command RES (software reset). The analog section is disabled (transmission of INFO 0) and the U interface awake detector ...
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Pending Activation This state results from a request for activation of the line, either from the terminal (INFO 1w) or from the layer-2 device (AR, AR2 or ARL). INFO 2 is then transmitted and the OCTAT-P waits for the responding ...
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INFO 1w and 1/2 are used for initialization and tests. The form of all INFO is shown in the following table: Name Direction INFO 0 Upstream Downstream INFO 1W Upstream INFO 1 Upstream INFO 2 Downstream 4 kHz burst rate ...
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Example of Activation and Deactivation An activation and deactivation procedure between an OCTAT-P and an IBC or ISAC mode over the U how the state machines of the respective modes interwork to facilitate activation and deactivation. ...
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Registers Description The monitor channel is used for programming local functions implemented in OCTAT-P IOM channel 0 only. Accesses to the registers are treated as local functions and therefore are marked with the code “1000” in the ...
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General Configuration Register – (Write) Address Format: bit 7 IC7D IC6D IC5D Initial Value Description: ICnD: BEM: 4.3 Bit Error Register – (Read) Address Format: bit 7 BEO7 BEO6 BEO5 Initial ...
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Line Delay Measurement of the U The delay of each U interface cable can be measured by one 8-bit counter with a PN programmable resolution 130 ns. The line delay time W the range up ...
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Data Sheet Transceiver No selected Transceiver No selected Transceiver No selected Transceiver No. 7 ...
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IRU 8 /LQH ,QWHUIDFHV 5HDG Address Format: bit7 DELAY7 DELAY6 DELAY5 DELAY4 DELAY3 DELAY2 DELAY1 DELAY0 Initial Value '(/$< Measured delay between U with a programmed resolution 130 ns. ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Ambient temperature under bias: PEB Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin ...
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Figure 5-2 Maximum Line Input Current 5.2 DC Characteristics All pins except LIna,b; XTAL1, 2 Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Input ...
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DC Characteristics (cont’ All pins except LIna,b; XTAL1, 2 Parameter Input leakage current high Input leakage current low LIna, b Operational supply current Transmitter output impedance Receiver ...
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Capacitances All pins except LIna, b Parameter Pin capacitance LIna,b Output capacitance against V SS XTAL1, 2 Recommended typical crystal parameters. Refer to Figure 3-5. Motional ...
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AC Characteristics testing: Inputs except XTAL1 are driven at 2.4 V for a logic “1” and at 0.4 V for a logic “0”. XTAL1 is driven ...
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Clocks CLK1 Parameter High phase of crystal/clock Low phase of crystal/clock Clock period CLK2 Parameter High phase of crystal/clock Low phase of crystal/clock Clock period CLK2 is directly derived from the oscillator clock and can drive ...
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Timing of the IOM • Figure 5-6 IOM Interface Timing with Double Data Rate DCL ® Data Sheet Interface ® 5-7 PEB 2096 Electrical Characteristics 04.99 ...
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Parameter Frame sync. hold Frame sync. setup Frame sync. high Frame sync. low Data delay to clock Data setup Data hold Superframe sync. setup Superframe sync. hold Data clock high Data clock low Data Sheet Electrical Characteristics Symbol Limit ...
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Figure 5-7 IOM -2 Interface Timing with Single Data Rate DCL ® Data Sheet Electrical Characteristics 5-9 PEB 2096 04.99 ...
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Figure 5-8 SSYNC Timing Note: A low at SSYNC input sets the U T-bit to high if SYNEN is programmed to high. 5.7 Boundary Scan Timing • Parameter Test clock period Test clock period low Test clock period high ...
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Figure 5-9 Boundary Scan Timing Data Sheet Electrical Characteristics 5-11 PEB 2096 04.99 ...
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U Frame Relation to FSC in Transmit Direction PN The LF-bit on the U interface appears T0 after the last but two (3 PN falling edge of DCL before FSC rising edge (Figure 5-10). • FSC DCL Llna, b ...
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FSC DCL Llna, b Figure 5-11 F-Bit Delay to FSC in Single Clock Mode oscillator periods + analog delay Analog delay < 1 oscillator period (15.36 MHz) Data Sheet Electrical Characteristics F-Bit T 0 0.5 oscillator periods ...
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Transceiver Characteristics A detailed transceiver architecture is shown in Figure 5-12. It comprises the transmitter output stages, the differential-to-single ended receiver input stage, the loop switch, the peak detector, and the threshold comparators. • Figure 5-12 Detailed Transceiver Architecture ...
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Power Supply Rejection Ratio (PSRR) The PSRR of the receiver is better than – frequencies below 100 kHz, decreasing per decade above 100 kHz. Noise Immunity The noise immunity target of the receiver is ...
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Package Outlines • P-MQFP-44 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 6-1 PEB 2096 Package Outlines Dimensions ...