PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 56

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
5.4
T
AC testing: Inputs except XTAL1 are driven at 2.4 V for a logic “1” and at 0.4 V for
•
Figure 5-4
Jitter
The clock input FSC is used as reference clock to provide the 768 kHz clock for the U
interface. In the case of a plesiochronous 15.36 MHz clock generated by an oscillator
with a maximum frequency deviation of
less than 20 ns peak-to-peak, as the PLL manages max. 0.5 oscillator period (32.5 ns)
in one IOM frame (in 125 s).
A
= 0 to 70 C;
V
DD
-
0.5
0.5
AC Characteristics
V
V
a logic “0”.
XTAL1 is driven at
Timing measurements are made at 2.0 V for a logic “1” and
at 0.8 V for a logic “0”.
TTL Input Level for all Inputs exept XTAL1
CMOS Input Level for XTAL1
TTL Output Level
V
DD
= 5 V
2.0
0.8
Test Points
5 %
V
DD
2.0
0.8
0.5 V for a logic “1” and 0.5 V for a logic “0”.
100 ppm, the clock FSC should have a jitter of
5-5
Device
Under
Test
Electrical Characteristics
C
Load
= 100
PEB 2096
ITS07329
pF
04.99
PN