PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 21

PEB2096HV31XT

Manufacturer Part Number
PEB2096HV31XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEB2096HV31XT

Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
2.2.3.2
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE St. 1149.1. Transitions on the pin TMS cause the TAP controller to
perform a state change.
The TAP controller supports 8 instructions:
• 5 instructions following the standard definition and
• 3 user specific instructions.
Code
0000
0001
0010
0011
11xx
1001
1010
1011
EXTEST is used to examine the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of TCK. When it has entered state “capture DR” the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of TCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both
activities are transparent to the system functionality.
Note: The input pin XTAL1 should not be evaluated.
Data Sheet
The input frequency (15.36 MHz) is not synchronous to TCK (6.25 MHz) which
causes unpredictable snap-shots on the pin XTAL1.
TAP Controller
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
User specific
User specific
User specific
External testing
Snap-shot testing
Bypass operation
Function
Internal testing
Reading ID code register
Continuous pulses on LIna and LInb
Continuous pulses on LIna
Continuous pulses on LInb
2-9
Functional Description
PEB 2096
04.99

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