PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 42
PEB2096HV31XT
Manufacturer Part Number
PEB2096HV31XT
Description
Manufacturer
Lantiq
Datasheet
1.PEB2096HV31XT.pdf
(67 pages)
Specifications of PEB2096HV31XT
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Data Sheet
•
Figure 3-8
Resynchron.
RSY
i2
i1
Unconditional Transitions Initiated by
Commands:
External Pins:
ARx = AR, AR2, ARL
DC
ARx,Al
i1
i3
OCTAT-P State Diagram
i1, i3
DR
RES, TM1, TM2
RST
ARx
i3
Synchronized
Pend.Deact.
Deactivated
Wait for DR
TIM
UAI
Activated
AR
Pend.Act.
DI
DI
Al
i0
i0
i0
i2
i4
i4
DC
ARx,Al
DC
ARx,Al
i0
DC
i1w, ARx
DC
ARx
i1
i3
DR
DR
DC
i1w
i0
i0
i0
i0
i3
i1
DC
DR
DR
DR
DR
3-14
TIM
Test Mode
it
DR
i
TM1
TM2
*
*)
refer to chapter Chapter 2.2
TM1
TM2
Operational Description
IOM
TIM
DR
i0
Reset
U
R
RES
*
OUT
RES
ind
i
X
State
RST
ITD04467
cmd
i
R
PEB 2096
IN
04.99
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