PEB2096HV31XT Lantiq, PEB2096HV31XT Datasheet - Page 15

• Manufacturer Part Number: PEB2096HV31XT
• Manufacturer: Lantiq

Specifications of PEB2096HV31XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEB 2096
Functional Description
S-channel bit is transmitted once in each direction in every fourth burst repetition period.
Hence the duplex S channel has a data rate of 1 kbit/s. It conveys test loop control
information from the LT to the TE/PT and reports of transmission errors from the TE/PT
to the LT. Bit 2 and bit 4 of the superframe are the T bits. This 2 kbit/s channel is
accessible via the C/I channel and may be used to carry the “available”/“blocked”
information sent by the D-channel arbiter of the PEB 20550, ELIC.
It is allowed to add a DC balancing bit to the burst, in order to decrease DC offset voltage
on the line after transmission of a CV in the M-bit position. The OCTAT-P transmits this
DC balancing bit when transmitting INFO 4 and when line characteristics indicate
potential decrease in performance.
The OCTAT-P scrambles B-channel data on the U
interface in order to ensure that the
PN
downstream receiver (e.g. ISAC-P TE) gets enough pulses for a reliable clock extraction
(flat continuous power density spectrum is provided) and no periodic patterns appear on
the line.
The scrambling is in accordance with CCITT V.27.
The coding technique used on the U interface is a half-bauded AMI code (with a 50 %
pulse width). A logical ‘0’ corresponds to a neutral level, logical ‘1s’ are coded as
alternate positive and negative pulses. Code violation (CV) is caused by two successive
pulses with the same polarity.
See Figure 2-2. The AMI coding includes always the data bits going on the U
interface
PN
in one direction. Thus there is a separate AMI coding unit for data downstream and one
for data upstream.
•
Figure 2-2
AMI Coding on the U
Interface
PN
Data Sheet
2-3
04.99