CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 43

• Manufacturer Part Number: CS8952-CQ
• Description: IC ETHNT 10/100 TXRX 5V 100-TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQ

• Mounting Type: Surface Mount
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 100-TQFP, 100-VQFP
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Ethernet
• Leaded Process Compatible: No
• No. Of Drivers: 6
• Interface Type: MII
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1205

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
11
10
9
8
7
6
BIT
DCR Rollover
FCCR Rollover
RECR Rollover
Remote Loopback
Fault
Reset Complete
Jabber Detect
NAME
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 1
Read/Write 0
TYPE
RESET
When set, an interrupt will be generated if the MSB in
the DCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the FCCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the RECR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the elastic
buffer in the PMA is under-run or over-run during
Remote Loopback. This should not occur for normal
length 802.3 frames.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated once the
digital and analog sections have been reset, and a
calibration cycle has been performed.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when a Jab-
ber condition is detected by the 10BASE-T MAU.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DESCRIPTION
CS8952
43