CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 78

• Manufacturer Part Number: CS8952-CQ
• Description: IC ETHNT 10/100 TXRX 5V 100-TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQ

• Mounting Type: Surface Mount
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 100-TQFP, 100-VQFP
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Ethernet
• Leaded Process Compatible: No
• No. Of Drivers: 6
• Interface Type: MII
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1205

TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
Media Interface Pins
RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7.
SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8.
TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4.
General Pins
CLK25 - 25 MHz Clock. Output, Pin 17.
RES - Reference Resistor. Input, Pin 86.
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These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output
waveform. The rise and fall times are symmetric.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer primary.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer primary.
PECL output pair receives 100 Mb/s NRZI-encoded data from an external optical module.
PECL input pair receives signal detection indication from an external optical module.
PECL output pair drives 100 Mb/s NRZI-encoded data to an external optical module.
A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference
transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode
Initialization pin (TCM) for more information on TX_CLK operating modes.
CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer
Configuration Register (address 17h).
This input should be connected to ground with a 4.99 k
for the biasing of internal analog circuits.
TXSLEW0 pin
floating
floating
floating
high
high
high
low
low
low
TXSLEW1 mode
floating
floating
floating
high
high
high
low
low
low
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
+/-1% series resistor. The resistor is needed
Rise/Fall time
0.5 ns
1.0 ns
1.5 ns
2.0 ns
2.5 ns
3.0 ns
3.5 ns
4.0 ns
4.5 ns
CS8952