CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 46

• Manufacturer Part Number: CS8952-CQ
• Description: IC ETHNT 10/100 TXRX 5V 100-TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQ

• Mounting Type: Surface Mount
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 100-TQFP, 100-VQFP
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Ethernet
• Leaded Process Compatible: No
• No. Of Drivers: 6
• Interface Type: MII
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1205

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BIT
Remote Loopback
Fault
Reset Complete
Jabber Detect
Auto-Neg Complete Read Only 0
Parallel Detection
Fault
Parallel Fail
NAME
Read Only 0
Read Only 0
Read Only 0
Read Only 0
Read Only 0
TYPE
RESET
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
When set, this bit indicates that the Elastic Buffer has
detected an over-run or an under-run condition. In
any case, the frame generating this fault will be ter-
minated.
This should never happen since the depth of the
elastic buffer (10 bits) is greater than twice the maxi-
mum number of bit times the receive and transmit
clocks may slip during a maximum length packet
assuming clock frequency tolerances of 100 ppm or
less.
When set, this bit indicates that the internal analog
calibration cycle has completed, and all analog and
digital circuitry is ready for normal operation.
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Basic Mode Status Register
(address 01h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
This bit is set when the auto-negotiation process has
completed. This is an indication that the Auto-Negoti-
ation Advertisement Register (address 04h), the
Auto-Negotiation Link Partner Ability Register
(address 05h), and the Auto-Negotiation Expansion
Register (address 06h) are valid.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
When set, this bit indicates an error condition in
which auto-negotiation has detected that unstable
10BASE-T or 100BASE-TX link signalling was
received. This bit is self-clearing.
This bit is the same as in the Auto-Negotiation
Expansion Register (address 06h)
When set, this bit indicates that a parallel detection
has occurred for a technology that is not currently
advertised by the local device.
DESCRIPTION
CS8952