PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet
PI7C8150BMAIE
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PI7C8150B Asynchronous 2-Port PCI-to-PCI Bridge 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Email: Internet: http://www.pericom.com REVISION 1.08 Fax: 408-435-1100 solutions@pericom.com ...
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... Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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REVISION HISTORY Date Revision Number 03/26/03 1.00 First Release of Data Sheet 05/14/03 1.01 06/10/03 1.02 06/25/03 1.03 07/31/03 1.031 Corrected MS0 and MS1 pin assignments on Table 2.4. MS0 should 10/20/03 1.04 Modified spacing on a few chapters. No ...
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This page intentionally left blank. ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 4 of 109 April 2009 – Revision 1.08 PI7C8150B ...
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TABLE OF CONTENTS 1 INTRODUCTION .............................................................................................................................. 11 2 SIGNAL DEFINITIONS ................................................................................................................... 12 2 ............................................................................................................................... 12 IGNAL YPES 2.2 S ........................................................................................................................................ 12 IGNALS 2.2.1 PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12 2.2.3 CLOCK SIGNALS ............................................................................................................... 15 2.2.4 MISCELLANEOUS SIGNALS........................................................................................... 16 ...
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MEMORY ADDRESS DECODING ........................................................................................... 43 4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 44 4.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 44 4.4 VGA SUPPORT........................................................................................................................... 45 4.4.1 VGA MODE......................................................................................................................... 46 4.4.2 VGA SNOOP MODE........................................................................................................... 46 5 ...
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SUPPORTED COMMANDS......................................................................................................... 73 13.1 PRIMARY INTERFACE ............................................................................................................. 73 13.2 SECONDARY INTERFACE....................................................................................................... 74 14 CONFIGURATION REGISTERS................................................................................................ 76 14.1 CONFIGURATION REGISTER ................................................................................................. 76 14.1.1 VENDOR ID REGISTER – OFFSET 00h......................................................................... 77 14.1.2 DEVICE ID REGISTER – OFFSET 00h .......................................................................... 77 14.1.3 ...
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RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 93 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 93 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 93 14.1.46 CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 93 14.1.47 NEXT ...
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LIST OF TABLES Table 2-1. Pin List – 208-pin FQFP............................................................................................................ 18 Table 2-2. Pin List – 256-pin PBGA............................................................................................................ 20 Table 3-1. PCI Transactions ........................................................................................................................ 22 Table 3-2. Write Transaction Forwarding .................................................................................................. 23 Table 3-3. Write Transaction Disconnect Address Boundaries................................................................... 26 ...
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This page intentionally left blank. ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 10 of 109 April 2009 – Revision 1.08 PI7C8150B ...
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INTRODUCTION Product Description The PI7C8150B is an enhanced PCI-to-PCI Bridge that will support asynchronous operation and is designed to be fully compliant with the PCI Local Bus Specification Revision 2.2. Both the primary and secondary interfaces are specified to ...
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SIGNAL DEFINITIONS 2.1 Signal Types Signal Type STS OD 2.2 Signals Note: Signal names that end with “_L” are active LOW. 2.2.1 PRIMARY BUS INTERFACE SIGNALS Name Pin # P_AD[31:0] 49, 50, 55, 57, 58, ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Name Pin # Pin # P_IRDY_L 82 T10 P_TRDY_L 83 R10 P_DEVSEL_L 84 P10 P_STOP_L 85 T11 P_LOCK_L 87 R11 P_IDSEL 65 P6 P_PERR_L 88 T12 P_SERR_L 89 P11 P_REQ_L 47 P2 P_GNT_L 46 R1 P_RESET_L ...
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Name Pin # P_M66EN 102 2.2.2 SECONDARY BUS INTERFACE SIGNALS Name Pin # S_AD[31:0] 206, 204, 203, 201, 200, 198, 197, 195, 192, 191, 189, 188, 186, 185, 183, 182, 165, 164, 162, 161, 159, 154, 152, 150, 147, 146, ...
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Name Pin # S_DEVSEL_L 175 S_STOP_L 173 S_LOCK_L 172 S_PERR_L 171 S_SERR_L 169 S_REQ_L[8: 207 S_GNT_L[8:0] 19, 18, 17, 16, 15, 14, 13, 11, 10 S_RESET_L 22 S_M66EN 153 S_CFN_L 23 2.2.3 ...
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Name Pin # S_CLKIN 21 S_CLKOUT[9:0] 42, 41, 39, 38, 36, 35, 33, 32, 30, 29 2.2.4 MISCELLANEOUS SIGNALS Name Pin # MSK_IN / 126 ASYNC_CLKIN P_VIO 124 S_VIO 135 BPCCE 44 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin # ...
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CFG66 / 125 SCAN_EN_H / CLK_RATE MS0, MS1 155, 106 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS Name Pin # GPIO[3:0] 24, 25, 27, 28 2.2.6 JTAG BOUNDARY SCAN SIGNALS Name Pin # TCK 133 TMS 132 TDO 130 TDI 129 ...
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POWER AND GROUND Name Pin # VDD 1, 26, 34, 40, 51, 53, 56, 62, 69, 75, 81, 91, 97, 103, 105, 108, 114, 120, 131, 139, 145, 151, 155, 157, 163, 170, 178, 184, 190, 196, 202, 208 ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Pin Number Name 33 S_CLKOUT[3] 35 S_CLKOUT[4] 37 VSS 39 S_CLKOUT[7] 41 S_CLKOUT[8] 43 P_RESET_L 45 P_CLK 47 P_REQ_L 49 P_AD[31] 51 VDD 53 VDD 55 P_AD[29] 57 P_AD[28] 59 VSS 61 P_AD[25] 63 P_AD[24] 65 ...
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Pin Number Name 157 VDD 159 S_AD[11] 161 S_AD[12] 163 VDD 165 S_AD[15] 167 S_CBE[1] 169 S_SERR_L 171 S_PERR_L 173 S_STOP_L 175 S_DEVSEL_L 177 S_IRDY_L 179 S_FRAME_L 181 VSS 183 S_AD[17] 185 S_AD[18] 187 VSS 189 S_AD[21] 191 S_AD[22] 193 ...
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Pin Pin Name Type Number Number F2 S_GNT_L[ VDD VSS P F9 F11 VSS P F12 F14 S_AD[3] TS F15 G1 S_GNT_L[ VDD VSS P G8 G10 VSS ...
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PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO’s for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables that ...
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PI7C8150B neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses. 3.2 SINGLE ADDRESS PHASE A 32-bit address uses a single address phase. This address is driven ...
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MEMORY WRITE TRANSACTIONS Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions. When PI7C8150B determines that a memory write transaction forwarded across the bridge, PI7C8150B asserts DEVSEL_L with medium timing and ...
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Section 3.8.3.2 provides detailed information about how PI7C8150B responds to target termination during posted write transactions. 3.5.2 MEMORY WRITE AND INVALIDATE Posted write forwarding is used for Memory Write and Invalidate transactions. If offset 74h bits [8:7] = 11, the ...
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If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to ...
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See Chapter 6 for information about how multiple posted and delayed write transactions are ordered. 3.5.6 FAST BACK-TO-BACK TRANSACTIONS PI7C8150B can recognize and post fast back-to-back write transactions. When PI7C8150B cannot accept the ...
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If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly important to retain the value of the byte enable bits during the data phase, use ...
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DELAYED READ REQUESTS PI7C8150B treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data ...
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For memory read transactions, PI7C8150B aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150B returns ...
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To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 ...
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PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150B must convert the configuration command to a ...
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Device Number 1Fh PI7C8150B can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints ...
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The PI7C8150B forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. 3.7.4 SPECIAL CYCLES The Type 1 configuration mechanism is used to ...
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Normal termination Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY_L or STOP_L assertion from the target. ...
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For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master latency timer expires and the PI7C8150B’s bus grant is de-asserted. The target terminates the transaction with a retry, disconnect, or target abort. If PI7C8150B is delivering ...
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Target disconnect Target abort PI7C8150B handles these terminations in different ways, depending on the type of transaction being performed. 3.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8150B initiates a delayed write transaction, the type of target termination received from the ...
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Target Termination Target Disconnect Target Abort Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C8150B initiates another write transaction to attempt to deliver the ...
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The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of system error conditions. ...
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A locked sequence is being propagated across PI7C8150B, and the read transaction is not a locked transaction. PI7C78150B is currently discarding previously pre-fetched read data. The target bus is locked and the write transaction is a locked transaction. Use more ...
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ADDRESS DECODING PI7C8150B uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode ...
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The master-enable bit also allows upstream forwarding of memory transactions set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O ...
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ISA MODE PI7C8150B supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C8150B inside the I/O address range in order to support mapping of I/O ...
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MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be pre-fetched but that can be conditionally pre-fetched based on command type should be mapped into this space. ...
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The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C8150B uses to determine when to forward memory commands. PI7C8150B forwards a memory transaction from the primary to the secondary interface if the transaction ...
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VGA MODE When a VGA-compatible device exists downstream from PI7C8150B, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C8150B is operating in VGA mode, it forwards downstream those transactions ...
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TRANSACTIONS GOVERNED BY ORDERING RULES Ordering relationships are established for the following classes of transactions crossing PI7C8150B: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they ...
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The following general ordering guidelines govern transactions crossing PI7C8150B: The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests ...
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Note that delayed completion transactions cross PI7C8150B in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. ...
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ERROR HANDLING PI7C8150B checks, forwards, and generates parity on ...
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PI7C8150B sets the detected parity error bit in the secondary status register. PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met: The SERR_L enable bit is set in the ...
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PI7C8150B forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE If the parity-error-response bit corresponding to the initiator bus is set, PI7C8150B asserts TRDY_L to the initiator and the transaction is not queued. If multiple data phases are requested, STOP_L is also asserted to cause a ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE PI7C8150B sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. Similarly, for ...
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POSTED WRITE TRANSACTIONS During downstream posted write transactions, when PI7C8150B responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: PI7C8150B asserts P_PERR_L two cycles after the data transfer, ...
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PI7C8150B has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. During upstream write transactions, when a data parity error is reported on the ...
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Primary Detected Transaction Type Parity Error Bit 1 Delayed Write 0 Delayed Write 0 Delayed Write 0 Delayed Write X = don’t care Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the ...
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Primary Data Transaction Type Parity Bit 0 Delayed Write X = don’t care Table 6-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: The PI7C8150B must ...
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P_PERR_L Transaction Type 1 Read 0 Posted Write 1 Posted Write 1 Posted Write 1 Posted Write 0 Delayed Write 2 0 Delayed Write 1 Delayed Write 1 Delayed Write X = don’t care 2 The parity error was detected ...
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The SERR_L enable bit must be set in the command register. Table 6-7. Assertion of P_SERR_L for Data Parity Errors P_SERR_L 1 (de-asserted (asserted don’t ...
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Delayed write data discarded after 2 received) Delayed read data cannot be transferred from target after 2 target retries received) Master timeout on delayed transaction The device-specific P_SERR_L status register reports the reason for the assertion of P_SERR_L. Most of ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When ...
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I/O Read induces master abort I/O Write induces master abort Memory Write induces master abort When PI7C8150B receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the ...
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When PI7C8150B receives a target abort or a master abort in response to a locked posted write transaction, PI7C8150B cannot pass back that status to the initiator. PI7C8150B asserts SERR_L on the initiator bus when a target abort or a ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN_L is ...
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If PI7C8150B detects that an initiator has failed to assert S_FRAME_L after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. To prevent bus contention, if the secondary PCI bus is idle, ...
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If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C8150B keeps the secondary bus grant asserted to a particular master until a new secondary ...
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To set asynchronous mode support, MS0 and MS1 must be configured accordingly: When MS0 and MS1 are pulled to HIGH during the deassertion of P_RST, PI7C8150B will go into asynchronous mode. The secondary clock outputs will then be derived from ...
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Input data field The bottom four bits of the output enable fields control whether each GPIO signal is input only or bi-directional. Each signal is controlled independently by a bit in each output enable control field ...
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Table 10-2. GPIO Serial Data Format Bit [1:0] [3:2] [5:4] [7:6] [8] [9] [10] [11] [12] [13] [14] [15] The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control the S_CLKOUT[3:0] outputs. If one ...
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To enable live insertion mode, the live insertion mode bit in the chip control register must be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO output enable control register. ...
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Current Status D3cold D0 PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges. 12 RESET This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 12.1 PRIMARY INTERFACE RESET ...
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When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150B remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 12.3 CHIP RESET The chip reset bit in ...
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P_CBE [3:0] 1010 1011 1100 1101 1110 1111 13.2 SECONDARY INTERFACE S_CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Command Action Configuration Read Type 0 Configuration Read: If the bridge’s IDSEL line ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE S_CBE[3:0] Command 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Page 75 of 109 ADVANCE INFORMATION Action I. Type 0 Configuration Write: Ignore II. ...
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CONFIGURATION REGISTERS PCI configuration defines a 64-byte space (configuration header) to define various attributes of PI7C8150B as shown below. 14.1 CONFIGURATION REGISTER 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Prefetchable Memory Limit I/O ...
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VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID 14.1.2 DEVICE ID REGISTER – OFFSET 00h Bit Function 31:16 Device ID 14.1.3 COMMAND REGISTER – OFFSET 04h Bit Function 0 I/O Space Enable Memory Space 1 Enable ...
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Bit Function Wait Cycle 7 Control P_SERR_L 8 enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.4 STATUS REGISTER – OFFSET 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz Capable 22 Reserved 23 Fast Back-to- Back Capable 24 ...
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Bit Function 30 Signaled System Error 31 Detected Parity Error 14.1.5 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 14.1.6 CLASS CODE REGISTER – OFFSET 08h Bit Function 15:8 Programming Interface 23:16 Sub-Class Code 31:24 Base Class Code ...
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PRIMARY BUS NUMBER REGISTSER – OFFSET 18h Bit Function 7:0 Primary Bus Number 14.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 15:8 Secondary Bus Number 14.1.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h Bit Function 23:16 Subordinate ...
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I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 11:8 32-bit Indicator 15:12 I/O Base Address [15:12] 14.1.16 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function 20:16 Reserved 21 66MHz Capable 22 Reserved Fast Back-to- 23 Back Capable Master Data ...
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MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 15:4 Memory Base Address [15:4] 14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h Bit Function 19:16 31:20 Memory Limit Address [31:20] 14.1.19 PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h Bit Function ...
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PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch Bit Function 31:0 Prefetchable Memory Limit Address, Upper ...
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INTERRUPT PIN REGISTER – OFFSET 3Ch Bit Function 15:8 Interrupt Pin 14.1.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch Bit Function 16 Parity Error Response 17 S_SERR_L enable 18 ISA enable 19 VGA enable 20 Reserved 21 Master Abort Mode ...
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Bit Function 22 Secondary Interface Reset 23 Fast Back-to- Back Enable 24 Primary Master Timeout 25 Secondary Master Timeout 26 Master Timeout Status 27 Discard Timer P_SERR_L enable 31-28 Reserved 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit ...
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Bit Function 4 Secondary Bus Prefetch Disable 5 Live Insertion Mode 7:6 Reserved 8 Chip Reset 10:9 Test Mode For All Counters at P and S1 15:11 Reserved 14.1.30 ARBITER CONTROL REGISTER – OFFSET 40h Bit Function 24:16 Arbiter Control ...
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EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit Function Memory Read 0 Flow Through Enable 1 Park 15:2 Reserved 14.1.32 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( Memory Base and Limit Enable ...
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UPSTREAM ( MEMORY BASE REGISTER – OFFSET 50h Bit Function 3:0 64 bit addressing Upstream 15:4 Memory Base Address 14.1.35 UPSTREAM ( MEMORY LIMIT REGISTER – OFFSET 50h Bit Function 19:16 64 bit addressing Upstream ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Bit Function Type Description Controls PI7C8150B’s ability to assert P_SERR_L when it is unable to transfer any read data from the target after 2 0: P_SERR_L is asserted if this event occurs and the SERR_L enable ...
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GPIO DATA AND CONTROL REGISTER – OFFSET 64h Bit Function GPIO Output 11:8 Write-1-to-Clear GPIO Output 15:12 Write-1-to-Set GPIO Output 19:16 Enable Write-1- to-Clear GPIO Output 23:20 Enable Write-1- to-Set 27:24 Reserved GPIO Input Data 31:28 Register 14.1.40 SECONDARY ...
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P_SERR_L STATUS REGISTER – OFFSET 68h Bit Function Address Parity 16 Error Posted Write 17 Data Parity Error Posted Write 18 Non-delivery Target Abort 19 during Posted Write Master Abort 20 during Posted Write Delayed Write 21 Non-delivery Delayed ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Bit Function Type Description Controls PI7C8150B’s detection mechanism for matching memory read retry cycles from the initiator on the secondary Secondary 0: exact matching for memory read retry cycles from initiator on the MEMR secondary interface ...
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Bit Function 15:12 Reserved 14.1.43 RETRY COUNTER REGISTER – OFFSET 78h Bit Function 31:0 Retry Counter 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function 15:0 Primary Timeout 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function Secondary ...
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SLOT NUMBER REGISTER – OFFSET B0h Bit Function Expansion Slot 20:16 Number 21 First in Chassis 23:22 Reserved 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function Chassis Number 31:24 Register 14.1.50 CAPABILITY ID REGISTER – OFFSET DCh Bit ...
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POWER MANAGEMENT DATA REGISTER – OFFSET E0h Bit Function 1:0 Power State 7:2 Reserved 8 PME# Enable 12:9 Data Select 14:13 Data Scale 15 PME status 14.1.54 CAPABILITY ID REGISTER – OFFSET E4h Bit Function 7:0 Capability ID 14.1.55 ...
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BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME_L signal bridge, there are a number of possibilities. Those possibilities are summarized in the table below: 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES Initiator Master on ...
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Again, the PAR signal corresponds to read data from the previous data phase cycle. 15.2.3 REPORTING PARITY ERRORS For all address phases parity error is detected, the error should be reported on the P_SERR_L signal by ...
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This mode of operation is valuable for design debugging and fault diagnosis since it permits examination ...
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The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant ...
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TAP TEST DATA REGISTERS The PI7C8150B contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most ...
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TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST_L pin. In addition, ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Boundary-Scan Pin Name Register Number 49 S_REQ_L[0] 50 S_REQ_L[1] 51 S_REQ_L[2] 52 S_REQ_L[3] 53 S_REQ_L[4] 54 S_REQ_L[5] 55 S_REQ_L[6] 56 S_REQ_L[7] 57 S_REQ_L[8] 58 S_GNT_L[0] 59 S_GNT_L[ S_GNT_L[2] 62 S_GNT_L[3] 63 S_GNT_L[4] 64 S_GNT_L[5] ...
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Boundary-Scan Register Number 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 17 ELECTRICAL AND TIMING ...
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DC SPECIFICATIONS Symbol Parameter V , Supply Voltage Input HIGH Voltage ih V Input LOW Voltage il V CMOS Input HIGH Voltage ih V CMOS Input LOW Voltage il V Input Pull-up Voltage ipu I ...
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AC SPECIFICATIONS Figure 17-1 Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal valid delay – bused signals ...
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TIMING Symbol Parameter T SKEW among S_CLKOUT[9:0] SKEW T DELAY between PCLK and S_CLKOUT[9:0] DELAY T P_CLK, S_CLKOUT[9:0] cycle time CYCLE T P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 17.6 POWER CONSUMPTION Parameter Power ...
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PACKAGE INFORMATION 18.1 208-PIN FQFP PACKAGE DIAGRAM Figure 18-1 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 208-pin FQFP Package Outline Page 107 of 109 April 2009 – Revision 1.08 PI7C8150B ...
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... PART NUMBER ORDERING INFORMATION Part Number PI7C8150BMA PI7C8150BND PI7C8150BMA-33 PI7C8150BND-33 PI7C8150BMAE PI7C8150BNDE PI7C8150BMAI PI7C8150BNDI PI7C8150BMAI-33 PI7C8150BNDI-33 PI7C8150BMAIE PI7C8150BNDIE ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 256-pin PBGA Package Outline http://www.pericom.com/packaging/mechanicals.php Speed Pin – Package 66 MHz 208 – FQFP 66 MHz 256 – PBGA 33 MHz 208 – ...
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: Page 109 of 109 April 2009 – Revision 1.08 PI7C8150B ...