PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet - Page 61

• Manufacturer Part Number: PI7C8150BMAIE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7
7.1
7.2
7.2.1
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
for specific events. The master timeout condition has a SERR_L enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
This chapter describes the use of the LOCK_L signal to implement exclusive access to a
target for transactions that cross PI7C8150B.
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when
a locked transaction crosses PI7C8150B. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This means
that a primary master can lock a primary target at the same time that a secondary master
locks a secondary target.
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B
For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts
LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target
lock has been achieved.
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
Locked transactions can cross PI7C8150B only in the downstream direction, from the
primary bus to the secondary bus.
EXCLUSIVE ACCESS
Delayed write data discarded after 2
received)
Delayed read data cannot be transferred from target after 2
target retries received)
Master timeout on delayed transaction
The PCI bus must be idle.
The LOCK_L signal must be de-asserted.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
24
(default) attempts to deliver (2
ADVANCE INFORMATION
April 2009 – Revision 1.08
24
(default) attempts (2
24
target retries
PI7C8150B
24