PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet - Page 50

• Manufacturer Part Number: PI7C8150BMAIE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
6.1
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
PI7C8150B checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150B always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C8150B
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150B implements the following:
This chapter provides detailed information about how PI7C8150B handles errors.
It also describes error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8150B checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150B detects an address parity error on the primary interface,
the following events occur:
When PI7C8150B detects an address parity error on the secondary interface, the following
events occur:
ERROR HANDLING
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
If the parity error response bit is set in the command register, PI7C8150B does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts the transaction if it is directed to or across PI7C8150B.
PI7C8150B sets the detected parity error bit in the status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
If the parity error response bit is set in the bridge control register, PI7C8150B does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts transaction if it is directed to or across PI7C8150B.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B