PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet - Page 58

• Manufacturer Part Number: PI7C8150BMAIE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Table 6-5. Assertion of P_PERR_L
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
conditions:
Primary
Parity Bit
0
X = don’t care
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following
P_PERR_L
1 (de-asserted)
1
0 (asserted)
The PI7C8150B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150B detects a data parity error on the primary bus or detects S_PERR_L
asserted during the completion phase of a downstream delayed write transaction on the
target (secondary) bus.
Parity
Data
Transaction Type
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Direction
Downstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
ADVANCE INFORMATION
April 2009 – Revision 1.08
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
Secondary Parity
Secondary Parity
Secondary Parity
Error Response
Error Response
Error Response
Primary /
Primary /
Primary/
PI7C8150B
Bits
Bits
Bits