PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet - Page 51

• Manufacturer Part Number: PI7C8150BMAIE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.2.1
6.2.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8150B attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8150B.
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8150B detects a data parity error during a Type 0 configuration write
transaction to PI7C8150B configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8150B asserts
P_TRDY_L and writes the data to the configuration register. PI7C8150B also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8150B does not assert
P_PERR_L.
PI7C8150B sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
READ TRANSACTIONS
When PI7C8150B detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L. For
downstream transactions, when PI7C8150B detects a read data parity error on the
secondary bus, the following events occur:
PI7C8150B sets the detected parity error bit in the secondary status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
PI7C8150B asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8150B sets the detected parity error bit in the secondary status register.
PI7C8150B sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
Page 51 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B