PI7C8150BMAIE Pericom Semiconductor, PI7C8150BMAIE Datasheet - Page 5

• Manufacturer Part Number: PI7C8150BMAIE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
1
2
3
4
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
INTRODUCTION .............................................................................................................................. 11
SIGNAL DEFINITIONS ................................................................................................................... 12
2.2.1
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
PCI BUS OPERATION ..................................................................................................................... 22
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.7.1
3.7.2
3.7.3
3.7.4
3.8.1
3.8.2
3.8.3
3.8.4
ADDRESS DECODING..................................................................................................................... 41
4.2.1
4.2.2
S
S
PIN LIST – 208-PIN FQFP .......................................................................................................... 18
PIN LIST – 256-BALL PBGA ..................................................................................................... 20
TYPES OF TRANSACTIONS..................................................................................................... 22
SINGLE ADDRESS PHASE ....................................................................................................... 23
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23
DATA PHASE ............................................................................................................................. 23
WRITE TRANSACTIONS .......................................................................................................... 23
READ TRANSACTIONS............................................................................................................ 27
CONFIGURATION TRANSACTIONS ...................................................................................... 30
TRANSACTION TERMINATION ............................................................................................. 34
ADDRESS RANGES ................................................................................................................... 41
I/O ADDRESS DECODING........................................................................................................ 41
IGNAL
IGNALS
PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12
CLOCK SIGNALS ............................................................................................................... 15
MISCELLANEOUS SIGNALS........................................................................................... 16
GENERAL PURPOSE I/O INTERFACE SIGNALS ........................................................ 17
JTAG BOUNDARY SCAN SIGNALS ................................................................................ 17
POWER AND GROUND..................................................................................................... 18
MEMORY WRITE TRANSACTIONS................................................................................ 24
MEMORY WRITE AND INVALIDATE ............................................................................ 25
DELAYED WRITE TRANSACTIONS............................................................................... 25
WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 26
BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 26
FAST BACK-TO-BACK TRANSACTIONS ....................................................................... 27
PREFETCHABLE READ TRANSACTIONS.................................................................... 27
NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 27
READ PREFETCH ADDRESS BOUNDARIES ............................................................... 28
DELAYED READ REQUESTS .......................................................................................... 29
DELAYED READ COMPLETION WITH TARGET ........................................................ 29
DELAYED READ COMPLETION ON INITIATOR BUS................................................ 29
FAST BACK-TO-BACK READ TRANSACTION ............................................................. 30
TYPE 0 ACCESS TO PI7C8150B....................................................................................... 31
TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 31
TYPE 1 TO TYPE 1 FORWARDING................................................................................. 33
SPECIAL CYCLES ............................................................................................................. 34
MASTER TERMINATION INITIATED BY PI7C8150B ................................................. 35
MASTER ABORT RECEIVED BY PI7C8150B ................................................................ 36
TARGET TERMINATION RECEIVED BY PI7C8150B.................................................. 36
TARGET TERMINATION INITIATED BY PI7C8150B.................................................. 39
I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 42
ISA MODE........................................................................................................................... 43
T
........................................................................................................................................ 12
YPES
............................................................................................................................... 12
Page 5 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B