LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 11

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V,,=2.7V-3.6V
V CCW=vCcwHl12~
erase, full chip erase, word/byte
configuration.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock)
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
The CUI does not occupy an addressable
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor
Figures 16 and 17 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the Vccw voltage IV,,,,,
the status register, identifier codes, or blocks are enabled.
Placing VCCWH,,2 on Vccw
erase, full chip erase, word/byte
configuration operations.
Device
commands into the CUI. Table 3 defines these commands.
3.5 Read Identifier Codes
3.6 Write
SHARI=
read
operations
identifier
the CUI additionally controls block
are selected
codes
or block within
enables successful block
operation
write timings are used.
Read operations from
by writing
write
write
and lock-bit
and lock-bit
outputs
the device
memory
specific
Write
and
the
LHFl6507
&-&I’
OOFFF
OFFFF
07002
01003
Olca?
01001
Oloca
oooQ4
oOaI3
00002
00001
00000
08003
08002
08001
Figure 4. Device Identifier Code Memory Map
‘: Address A-1 don’t care.
1 Parameter Block 5 Lock Configuration Code 1
“--j-------------ii_------------------
:
--~-----------------------------------
-------**--T-------i------------------
:.
----*---,,,---*,--,,----1--------------
Parameter Block 0 Lock Confieuration Code
‘.
‘L Reserved ‘Ear F&&Implementation
Main Block 0 Lock Configuration Code
Boot Block 1 Lock Configuration Code
Permanent Lock Configuration Code
Reserved’ for Future IinpIementation
Reserved: for Future ImpIementation
Rese&d for F&ure Implementation
Reserved: for Future implementation
Reserved f& Future hplefnentation
Reserv&‘forFuture
Reserved for Future Implementation
(Parameter Blocks 1 through 4)
(Main Blocks 1 through 29)
:
yl for Future Zmp+nentation
________-_-____*__--_*_____
d: for Future hnphm&tion
Bottom Boot
Implementation
&rameter Biock 5 i
Main Block 0
Boot FJtixk I :
Rev. 1.2
9