LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 8

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

'Qo-DQI,
RYlBY#
SHARP
BYTE#
Symbol
A,-‘%
vccw
GND
WE#
WP#
“cc
CE#
RP#
OE#
NC
A-1
9
&!I!#&
OU’lJJUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Tee
DEVICE POWER SUPPLY: Do not float any power pins. With Vc,+V,,O,
the flash memory are inhibited. Device operations at invalid V,, voltage (see 6.2.3 DC
Characteristics) produce spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
A12-A,g: Boot and Parameter Block Address.
DATA INPUT/OUTPUTS:
during memory array, status register and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle. DQs-DQ,,
changes A-, address input.
CHIP ENABLE:
CE#-high deselects the device and reduces power consumption to standby levels.
RESET: Resets the device internal automation. RP#-high enables normal operation. When driven
low, RP# inhibits write operations which provides data protection during power transitions. Exit
from reset mode sets the device to read array mode. RP# must be V,, during power-up.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WRITE PROTECT: When WP# is V,,, boot blocks cannot be written or erased. When WP# is
V,, locked boot blocls can not be written or erased. WP# is not affected parameter and main
blocks.
BYTE ENABLE: BYTE# V, places device in byte mode (x8). All data is then input or output on
DQ,,,
input buffer.
READY/BUSY#:
internal operation (block erase, full chip erase, word/byte write or lock-bit configuration).
RY/BY#-high
and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode.
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE
CONFIGURATION
configuring lock-bits. With V,cwlV,,,,,
chip erase, word/byte write and lock-bit configuration with an invalid V,,
Characteristics) produce spurious results and should not be attempted. Applying 12Vti.6V
V,,,
may be connected to 12VkO.6V for a total of 80 hours maximum.
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A-,: Lower address input while BYTES is V,. A-, pin changes DQ,, pin while BYTE# is VI,.
A,5-A,g: Main Block Address.
during erase/write can only be done for a maximum of 1000 cycles on each block. Vccw
and DQ8-r5 float. BYTE# V,, places the device in word mode (x16), and turns off the A-,
Z indicates that the WSM is ready for new commands, block erase is suspended,
Activates the device’s control logic, input buffers, decoders and sense amplifiers.
Indicates the status of the internal WSM. When low, the WSM is performing an
POWER SUPPLY: For erasing array blocks, writing words/bytes or
Table 1. Pin Descriptions
pins are not used while byte mode (BYTE#=V,).
Inputs data and commands during CUI write cycles; outputs data
LHF16507
Name and Function
memory contents cannot be altered. Block erase, full
WRITE OR LOCK-BIT
Then, DQls pin
(see 6.2.3 DC
all write attempts to
Rev. 1.2
to
6