LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 27

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions.
toggle during system reset.
5.2 RY/BY# and WSM Polling
RY/BY# is an open drain output that should be connected
to V,, by a pull up resistor to provides a hardware method
of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
bit configuration commands and returns to V,,
RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
SHARI=
occur.
POWERGOOD
should also
(while
LHFl6507
requires that the printed
voltage spikes and overshoots.
Block erase, full chip erase, word/byte write and lock-bit
configuration are not guaranteed if Vccw falls outside of a
valid VCCWH1,2 range, V,,
register bit SR.3 is set to “1” along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V, during block erase, full chip erase, word/byte write
or lock-bit configuration, RY/BY#
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command
operation is restored. Device power-off or RP# transitions
to V, clear the status register.
The CUI latches commands issued by system software and
is not altered by Vccw
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V,, transitions below V,,,.
5.3 Power Supply Decoupling
Flash memory power switching
careful device decoupling. System designers are interested
in three supply current issues; standby current levels.
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a O.lpF ceramic capacitor
connected between its V,,
Vccw
capacitors should be placed as close as possible to package
leads. Additionally,
electrolytic capacitor should be placed at the array’s power
supply connection between V,,
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 VCCW Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
attention to the Vccw
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V,,
Vccw supply traces and decoupling will decrease Vccw
5.5 VCC, VCCW, RP# Transitions
3.6V range, or RP##V,,.
and GND. These high-frequency,
sequence must be repeated after normal
for every eight devices, a 4.7nF
Power supply trace. The Vccw pin
If V,,w
or CE# transitions
falls outside of a valid 2.7V-
circuit board designer pay
and GND and between its
error is detected, status
characteristics
power bus. Adequate
and GND. The bulk
will remain low until
low inductance
or WSM
Rev. 1.2
require
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