LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 9

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F160BJI-EBTL70
on-chip WSM to manage block erase, full chip erase,
word/byte write and lock-bit configuration functions. It
allows for: 100% l-IL-level
supplies during block erase, full chip erase, word/byte
write and lock-bit configuration, and minimal processor
overhead with RAM-like
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier
through the CUI independent of the V,,,
voltage on Vccw enables successful block erase, full chip
erase, word/byte
functions associated with altering memory contents-block
erase, full
configuration, status and identifier codes-are accessed via
the CUI and verified through the status register.
Commands are written
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
SHARI=
chip
write and lock-bit
erase,
interface timings.
using standard microprocessor
word/byte
control inputs, fixed power
Flash memory includes an
codes can be accessed
and margining of data.
write
configurations.
write,
voltage. High
and lock-bit
lock-bit
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Figure 3. Memory Map
JKW18KB
4KW/8KB
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4KW/8KB
32KWHKB
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32KW/64KB
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Bottom Boot
Parameter Block
Parameter Block
Parameter Block
Parameter
Parameter
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Main Block
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Rev. 1.2
7