LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 28

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

battery
battery life because data is retained when system power is
removed.
resets the CUI to read array mode at power-up.
both WE# and CE# must be low for a command write,
driving either to V,, will inhibit writes. The GUI’s two-
of protection against data alteration.
In-system
inadvertent data alteration. The device is disabled while
RP#=V,
5.7 Power Dissipation
When designing portable systems, designers must consider
operation, but also for data retention during system idle
time. Flash memory’s
5.6 Power-Up/Down Protection
The device is designed to offer protection
accidental block erase, full chip erase, word/byte write or
lock-bit
power-up, the device is indifferent as to which power
supply (Vccw
A system designer must guard against spurious writes for
V,,
step command sequence architecture provides added level
SHARP
voltages above VLKO when Vccw
power
configuration
regardless of its control inputs state.
block
or V,,)
consumption
lock and unlock
during power transitions.
powers-up first. Internal circuitry
nonvolatility
not only during device
capability prevents
increases usable
is active. Since
against
Upon
LHFl6507
memory
protecting all blocks. When the RP# is kept low during
power up and power down sequence such as voltage
transition, write operation on the flash memory is disabled,
write protecting all blocks. For the details of RP# control,
refer to the specification. (See chapter 5.6 and 6.2.7.)
When the level of Vccw is lower than VcCwLK (lockout
voltage), write operation on the flash memory is disabled.
All blocks are locked and the data in the blocks are
completely write protected. For the lockout voltage, refer
to the specification. (See chapter 62.3.)
3) Data protection through RP#
When the RP# is kept low during read mode, the flash
2) Data protection through Vccw
When a lock bit is set, the corresponding block (includes
the 2 boot blocks) is protected against overwriting.
setting a WP# to low, only ‘the 2 boot blocks can be
protected against overwriting.
flash memory space can be divided into the program
section (locked
section). The permanent lock bit can be used to prevent
false block
setting/resetting lock-bit, refer to the specification. (See
chapter 4.10 and 4.11.)
5.8 Data Protection Method
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands, causing undesired memory updating. Ta
protect the data stored in the flash memory against
unwanted overwriting,
memory should have the following write protect designs,
as appropriate:
1) Protecting data in specific block
will
bit setting. For further
be deep-power-down
section)
systems operating with the flash
and data section (unlocked
By using this feature, the
mode, then write
information
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