TDA5230XT Infineon Technologies, TDA5230XT Datasheet - Page 128

• Manufacturer Part Number: TDA5230XT
• Manufacturer: Infineon Technologies

Specifications of TDA5230XT

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 9.7mm
• Lead Free Status / Rohs Status: Compliant

Read Register
Figure 66
To read from the device, the chip must be selected first. Therefore, the master must set
the NCS line to low. After this, the instruction byte and the address byte are shifted in on
SDI and stored in the internal instruction and address register. The data byte at this
address is then shifted out on SDO. After completing the read operation the master sets
the NCS line to high.
Write Register
Figure 67
To write to the device, the chip must be selected first. Therefore the master must set the
NCS line to low. After this, the instruction byte and the address byte are shifted in on SDI
and stored in the internal instruction and address register. The following data byte is then
stored at this address.
After completing the write operation, the master sets the NCS line to high.
Use of the SPI Trace Registers:
The received address byte is stored into the register SPIAT and the received data byte
is stored into the register SPIDT. These two trace registers are readable. Therefore, an
external controller is able to check the correct address and data transmission by reading
out these two registers after each write instruction. The trace registers are updated at
every write instruction, so only the last transmission can be checked by a read out of
these two registers.
Data Sheet
NCS
SCK
SDO
SDI
SDO
NCS
SCK
SDI
high impedance Z
high impedance Z
I7
1
I7
1
I6
I6
I5
I5
Instruction
I4
Instruction
I4
I3
I3
I2
Read Register
Write Register
I2
I1
I1
I0
8
I0
A7 A6
8
1
A7 A6
1
Register Address
A5 A4
Register Address
A5 A4
Frame
Frame
A3 A2 A1 A0
A3 A2 A1 A0
8
D7 D6 D5 D4
8
1
D7 D6 D5 D4
1
Data Out
Data Byte
D3 D2 D1
D3 D2
D1 D0
D0
8
124
8
I7
1
I6
I5
I7
Instruction
1
I4
I6
I3
I5
Instruction
I2
I4
I1
I3
I0
I2
8
A7 A6
1
I1
I0
8
Register Address
A5 A4
A7 A6
1
Frame
A3 A2 A1 A0
Functional Description
Register Address
A5 A4
Frame
Version 4.0, 2007-06-01
A3 A2 A1 A0
8
D7 D6 D5 D4
1
8
D7 D6 D5 D4
Data Out
1
D3 D2 D1 D0
Data Byte
TDA523x
D3 D2
8
D1 D0
8