TDA5230XT Infineon Technologies, TDA5230XT Datasheet - Page 47

• Manufacturer Part Number: TDA5230XT
• Manufacturer: Infineon Technologies

Specifications of TDA5230XT

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 9.7mm
• Lead Free Status / Rohs Status: Compliant

Notes to Self Polling Modes State diagrams
1.) Idle: The state Idle is left, when the signal RX-RUN, which enables the receiver unit,
2. Wait: Wait until the start up sequencer has finished powering up the receiver unit.
3.) Init Loop Counter: The loop counter is reset to Channel 1 of configuration A. The
4. Modulation Switching CFG A: The receiver unit is set to the modulation type
5.) Init with CFG A: The receiver unit is initialized with the settings given in
6.) Load S1R1 channel: The receive channel is set according to the PLL settings given
7. WU Search CFG A: As determined by the selected Self Polling Mode scheme
8.) Store Channel: In this state, the currently selected receive channel (e.g. S1/R1) is
9.) Compare: If the loop counter equals the number of channels selected by the SFR
10.)Increment Loop Counter: In this state, the loop counter is incremented.
11.)Load S2R2/S3R3 Channel: The receive channel is set to the PLL settings given by
2.4.5.6
In Self Polling Mode, the chip is able to automatically change the type of modulation
once a wake up criterion has been satisfied in a received data stream. The type of
modulation used in the different operational modes is selected by the SFR control bits
MT, the types are shown in the following register table.
Data Sheet
is set by the Polling Timer Unit. T
state of the loop counter determines the selected channel.
defined in the SFR control bit MT.
Configuration A.
in register ARFPLL1 and waits for about 40µs (9*64/f
defined by the SFR control bits SPMSEL and PERMWUSEN, the corresponding WU
search scheme is activated.
If the search for the fulfillment of a wake up criterion complicated successfully, the
current receive channel is stored by entering the state Store Channel. Otherwise,
the next state is Compare.
stored as the actual channel in the register RFPLLAC. The chip resumes operation
in Run Mode Self Polling afterwards.
control bit ANOC, the next state of the chip will be the Idle state, unless dual
configuration is enabled by the SFR control bit DCE. In this case, the next state will
be Init Loop Counter in
in the Increment Loop Counter state.
the register ARFPLL2 and ARFPLL3 respectively and waits for about
40µs(9*64/fsys).
Automatic Modulation Switching
Figure 21
. In all other cases, the chip resumes operation
43
sys
).
Functional Description
Version 4.0, 2007-06-01
TDA523x