CY7C09189V-12AC Cypress Semiconductor Corp, CY7C09189V-12AC Datasheet - Page 10

• Manufacturer Part Number: CY7C09189V-12AC
• Description: SRAM Chip Sync Dual 3.3V 576K-Bit 64K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09189V-12AC

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 576 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 16 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Document #: 38-06043 Rev. *B
Switching Waveforms
Pipelined Read-to-Write-to-Read (OE = V
Pipelined Read-to-Write-to-Read (OE Controlled)
Notes:
26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
27. CE
28. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
ADDRESS
ADDRESS
DATA
DATA
DATA
DATA
0
and ADS = V
CLK
R/W
CLK
R/W
CE
CE
CE
CE
OUT
OUT
OE
IN
IN
0
1
0
1
t
t
t
t
t
t
SW
SC
SA
SW
SC
SA
IL
; CE
1
A
A
, CNTEN, and CNTRST = V
n
n
t
t
CH2
CH2
(continued)
t
t
CYC2
t
t
t
CYC2
t
t
t
HW
HC
HW
HA
HC
HA
t
t
CL2
CL2
A
READ
A
READ
n+1
n+1
t
t
CD2
CD2
IL
IH
)
.
[19, 26, 27, 28]
Q
t
t
SW
OHZ
n
[19, 26, 27, 28]
Q
n
t
SW
t
SD
D
A
A
n+2
n+2
t
n+2
HW
t
t
CKHZ
NO OPERATION
HD
t
HW
t
WRITE
SD
A
D
A
D
n+3
n+3
n+2
n+2
t
HD
WRITE
CY7C09079V/89V/99V
CY7C09179V/89V/99V
A
A
n+4
n+3
t
t
CKLZ
CKLZ
READ
READ
A
A
n+5
n+4
Page 10 of 18
t
t
CD2
CD2
Q
n+4
Q
n+3
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