CY7C09189V-12AC Cypress Semiconductor Corp, CY7C09189V-12AC Datasheet - Page 15

• Manufacturer Part Number: CY7C09189V-12AC
• Description: SRAM Chip Sync Dual 3.3V 576K-Bit 64K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09189V-12AC

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 576 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 16 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Document #: 38-06043 Rev. *B
Read/Write and Enable Operation
Address Counter Control Operation
Notes:
34. “X” = “Don’t Care”, “H” = V
35. ADS, CNTEN, CNTRST = “Don’t Care.”
36. OE is an asynchronous input signal.
37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38. CE
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE
Address
OE
A
X
X
X
X
X
X
H
L
0
n
and OE = V
Previous
Address
IL
A
A
X
X
CLK
; CE
n
n
X
1
and R/W = V
IH
, “L” = V
CLK
Inputs
CE
IL
IH
H
X
L
L
L
.
ADS
.
0
0
H
H
X
L
and CE
CNTEN
1
.
X
X
H
L
[34, 35, 36]
CE
H
H
H
X
L
[34, 38, 39, 40]
1
L
H
H
H
CNTRST
R/W
X
X
H
X
L
D
D
D
D
out(0)
out(n)
out(n)
out(n+1)
I/O
High-Z
High-Z
D
D
High-Z
IN
OUT
Outputs
I/O
Increment
0
Mode
Reset
Load
Hold
–I/O
9
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Deselected
Deselected
Write
Read
Outputs Disabled
[37]
Operation
[37]
[37]
Operation
Page 15 of 18
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