CY7C09189V-12AC Cypress Semiconductor Corp, CY7C09189V-12AC Datasheet - Page 8

• Manufacturer Part Number: CY7C09189V-12AC
• Description: SRAM Chip Sync Dual 3.3V 576K-Bit 64K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09189V-12AC

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 576 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 16 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Document #: 38-06043 Rev. *B
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes:
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = V
18. The output is disabled (high-impedance state) by CE
19. Addresses do not have to be accessed sequentially since ADS = V
ADDRESS
ADDRESS
DATA
DATA
IL
, CNTEN and CNTRST = V
CLK
R/W
CE
CE
OUT
CLK
R/W
CE
CE
OE
OUT
OE
0
1
0
1
t
t
t
SC
SW
SA
t
t
t
SC
SW
SA
A
A
n
n
(continued)
t
t
t
t
IH
HC
HW
HA
t
t
t
CH2
t
HC
HW
HA
CH1
.
t
1 Latency
CKLZ
t
CD1
t
CYC2
t
CYC1
t
CKLZ
0
t
=V
t
CL2
CL1
IH
or CE
A
A
n+1
n+1
IH
1
IL
)
[16, 17, 18, 19]
= V
IL
)
t
Q
DC
[16, 17, 18, 19]
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
t
n
CD2
IL
following the next rising edge of the clock.
Q
A
n
A
n+2
n+2
Q
t
OHZ
n+1
t
DC
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Q
t
t
t
SC
OE
SC
t
n+1
t
OLZ
OHZ
A
A
n+3
n+3
t
OLZ
Q
t
DC
t
n+2
t
HC
HC
t
OE
t
CKHZ
Page 8 of 18
Q
n+2
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