CY7C09189V-12AC Cypress Semiconductor Corp, CY7C09189V-12AC Datasheet - Page 4

• Manufacturer Part Number: CY7C09189V-12AC
• Description: SRAM Chip Sync Dual 3.3V 576K-Bit 64K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09189V-12AC

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 576 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 16 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Document #: 38-06043 Rev. *B
Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
Ambient Temperature with Power Applied ..–55
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
DC Input Voltage......................................–0.5V to V
Notes:
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
GND
NC
V
0L
CC
Left Port
0L
0L
L
–A
L
L
L
–I/O
,CE
16L
L
L
1L
L
8L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
Right Port
0R
0R
0R
R
–A
R
R
R
–I/O
,CE
16R
[10]
R
1R
R
R
8R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
their active states (CE
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
°
°
C to +150
C to +125
0
–A
CC
CC
14
0
+0.5V
+0.5V
≤ V
for 32K; A
0
°
°
IL
–I/O
C
C
and CE
7
for x8 devices; I/O
0
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
Operating Range
–A
Commercial
Industrial
1
15
≥ V
Range
for 64K; and A
Description
IH
).
[11]
0
–I/O
0
–A
8
–40
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Temperature
0
for x9 devices).
16
°
Ambient
C to +70
°
for 128K devices).
C to +85
0
AND CE
°
C
°
C
1
must be asserted to
3.3V ± 300 mV
3.3V ± 300 mV
Page 4 of 18
V
MAX
CC
.
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