CY7C09189V-12AC Cypress Semiconductor Corp, CY7C09189V-12AC Datasheet - Page 9

• Manufacturer Part Number: CY7C09189V-12AC
• Description: SRAM Chip Sync Dual 3.3V 576K-Bit 64K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09189V-12AC

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 576 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 16 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Document #: 38-06043 Rev. *B
Switching Waveforms
Bank Select Pipelined Read
-
Left Port Write to Flow-Through Right Port Read
Notes:
ADDRESS
ADDRESS
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS
21. OE and ADS = V
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE
24. OE = V
25. It t
DATA
DATA
ADDRESS
ADDRESS
= ADDRESS
until t
DATA
CCS
0
DATA
CE
CE
OUT(B2)
OUT(B1)
and ADS = V
CCS
CLK
≤ maximum specified, then data from right port READ is not valid until the maximum specified for t
CLK
R/W
CLK
R/W
IL
OUTR
0(B1)
0(B2)
(B1)
(B2)
for the right port, which is being read from. OE = V
+ t
INL
L
R
R
R
L
L
L
CD1
(B2)
. t
.
IL
t
t
t
t
IL
CWDD
SA
SC
SA
SC
; CE
; CE
1(B1)
1
does not apply in this case.
t
t
t
, CNTEN, and CNTRST = V
SW
SD
SA
A
A
, CE
0
0
t
CH2
MATCH
1(B2)
VALID
(continued)
[20, 21]
t
t
, R/W, CNTEN, and CNTRST = V
t
t
SW
SA
t
t
t
t
MATCH
CYC2
CCS
HC
HC
HA
HA
t
DC
t
CL2
t
t
t
t
HW
HA
t
HW
HA
HD
A
A
1
1
t
IH
CWDD
t
.
CD2
t
CD1
IH
for the left port, which is being written to.
[22, 23, 24, 25]
t
SC
D
t
0
IH
SC
.
A
A
2
2
t
t
DC
HC
t
HC
t
CD2
MATCH
VALID
NO
D
MATCH
A
A
1
3
t
NO
3
DC
t
t
CKLZ
CKHZ
t
t
CD2
DC
CWDD
. If t
CY7C09079V/89V/99V
CY7C09179V/89V/99V
CCS
t
CD1
>maximum specified, then data is not valid
D
A
A
4
2
4
t
t
t
CKHZ
CD2
CKLZ
D
3
A
A
Page 9 of 18
VALID
5
t
5
CKLZ
t
t
CKHZ
CD2
(B1)
D
4
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