MT90840AP Zarlink, MT90840AP Datasheet - Page 10

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Transmit Path
The Transmit Path is from the serial inputs, through the Transmit (Tx) Path Data Memory, to the parallel outputs
(PDo0-7). This path is controlled by the contents of the Tx Connection Memory. The Tx Connection Memory is
programmed, for each output time slot, with the address-value of the source channel to be read out of the Tx Data
Memory. Up to 512 channels of serial input can be switched to up to 2430 channels of parallel output.
Transmit Path Connection Memory
The Tx Path Connection Memory is structured as 2430 words of 16 bits. This supports up to 2430 DS0 channels for
parallel rates up to 19.44 Mbyte/s (155 Mbps). The Tx Path Connection Memory is accessed as two-sub memories:
High and Low. The Connection Memory Low (2430 X 8) is the low byte of the word, and is programmed with the
address-value of the serial-input source channel. The Connection Memory High (2430 x 8) is the high byte of the
word. Connection Memory High holds the high-order bit(s) of the source address-value, and is also programmed to
control per-channel functions such as output driver-enable and programmable control outputs.
PCKR
PPFRi
PDi0-7
PCKR or PCKT
(TCP bit = 0)
PPFTi/o
(PPFP bit =1)
PDo0-7
Notes: In TM1, 2 and 4 PPFRi and PPFT are not simultaneous.
Terminal count “n” = 2429, 2047, or 809.
Ch. n-2
Ch. n-2
Ch. n-1
Figure 4 - Parallel Data Port Functional Timing
Ch. n-1
Frame Boundary Established by PPFRi
Frame Boundary Established by PPFTi/o
Zarlink Semiconductor Inc.
Ch. n
Ch. n
MT90840
10
Ch. 0
Ch. 0
Ch. 1
Ch. 1
Ch. 2
Ch. 2
Data Sheet