MT90840AP Zarlink, MT90840AP Datasheet - Page 38

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Alarm Status Register (ALS) - READ/WRITE
MSK3-0
PPCE
RXPAA
TXPAA
FSA
Note:
MSKn is set HIGH, the corresponding interrupt source is enabled, and the IRQ pin will respond to that interrupt source; if set
LOW, the corresponding interrupt source is masked. When masked, an interrupt source will not assert the IRQ pin, but will still
set the ALS register bit. On system power-up, all interrupts are masked. Writes to the ALS register clear the low nibble
(interrupt source bits) regardless of the data written.
of PCKR clock cycles between PPFRi frame sync signals on the Receive parallel port. The numbers of clock cycles expected
depends on the parallel port rate selected in the IMS Register (2430, 2048, or 810 clock cycles). The absence of PPFRi for one
or more frames will not cause an interrupt (allowing free-run operation), but the PPCE bit will go HIGH if PPFRi occurs
anywhere but on an expected frame boundary.
reference goes out of phase relative to the parallel port clock (PCKR). A rising edge on the RXPAA bit indicates that the MT90840
has adjusted the position of F0o and SPCKo, and a data slip at the serial port has occurred. Note that a CPU write to the RPCM
memory as RXPAA goes HIGH (in TM2) may be corrupted. In TM2 with SFDI = 1, a rising edge on the RXPAA bit indicates that
the F0i input is out of phase with PPFRi, implying a failure in the timing supplied by the controlling (TM2 with SFDI = 0)
MT90840. When not in TM2 the RXPAA bit may be continuously asserted, and therefore should be masked by setting MSK2 LOW,
and ignored.
TX Phase Alignment Alarm. Used in TM1 operation. The TXPAA bit goes HIGH whenever the PCKT clock input goes out of
Frame Slip on Elastic Buffer. Used in TM1 operation. The FSA bit goes HIGH when either an overflow or underun condition on
cleared by writing the mask bits (ALS high nibble), regardless of the data written.
Mask Alarm Bits 3-0. These bits mask the specific interrupt source bits. MSK3 masks PPCE, MSK2 masks RXPAA, etc. If
Parallel Port Frame Counter Error. Used in all timing modes. The PPCE bit goes HIGH whenever there is an incorrect number
RX Phase Alignment Alarm. Used in TM2 operation, when INTCLK = 0. The RXPAA bit goes HIGH whenever the C4/8 input
The interrupt source bits are latched, and remain high until cleared by the CPU. The interrupt source bits (ALS low nibble) are
phase relative to the C4/8 clock. A rising edge on the TXPAA bit indicates that the MT90840 has adjusted the position of
PPFTo, and a data slip at the TX parallel port output has occurred. Note that a CPU write to the TPCM memory as TXPAA goes
HIGH (in TM1) may be corrupted. In TM1 with PFDI = 1, a rising edge on the TXPAA bit indicates that the PPFTi input is out of
phase with F0i, implying a failure in the timing supplied by the controlling (TM1 with PFDI=0) MT90840.
the Receive parallel port’s elastic buffer has been detected. A rising edge on the FSA bit indicates that a frame of data from the
RX parallel port has been dropped, or repeated. In TM2, TM3, and TM4 the user should mask this bit by setting MSK0 LOW.
MSK3
7
MSK2
6
MSK1
5
MSK0
4
Zarlink Semiconductor Inc.
PPCE
3
MT90840
RXPAA
38
2
TXPAA
1
FSA
0
Data Sheet