MT90840AP Zarlink, MT90840AP Datasheet - Page 29

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

MT90840
Data Sheet
CPU Memory Write Operation (Write Pipeline)
CPU write access to the Connection Memories (TPCM and RPCM) must also be multiplexed with the TDM port
accesses. To allow faster CPU write operations, the MT90840 has a transparent single-byte write pipeline. CPU
write accesses are performed in the same manner as reads, with the Control Register programmed to specify the
memory and page. The DTA pin is asserted by the MT90840 to indicate that the CPU data has been latched into
the device. An isolated write operation will receive a register-speed DTA, as the data is latched into the transparent
write pipeline to await the next free TDM clock edge. A second write will not receive a DTA acknowledgment until
the first write has exited the internal write pipeline. The DTA response time on the second write is a function of the
memory chosen for the write currently in the pipeline, and is given in the AC Electrical Characteristics section.
DTA Operation and TDM Clocks
If the CPU tries to read a memory for which the necessary TDM clock is not present, the DTA pin will not be
asserted. If the CPU tries to write a memory for which the necessary TDM clock is not present, the DTA pin will be
asserted (as the data is stored in the write-pipeline) but the next CPU access will not see DTA asserted. No clocks
are necessary for register accesses (but if the write-pipeline is hung, the registers cannot be accessed). If the
MT90840 is hung due to a CPU read of a memory with a missing clock, the hang can be cleared by ending the read
access. If the MT90840 is hung due to a CPU write to a memory with a missing clock, the hang can be cleared by
applying a hardware RESET to the MT90840.
Detecting Clock Presence
After it is set, the BPE bit is cleared within 2 frames of the C4/8 clock (i.e. within 250 µsec). If this bit is cleared by
the MT90840, the CPU can deduce that the C4/8 clock is present. In TM3, in TM4, and in TM2 with INTCLK
asserted, C4/8 is internally generated from PCKR, and if the BPE bit is cleared by the MT90840, the CPU can
deduce that the PCKR clock is present.
Clock Quality and TM1 TPCM Access Integrity
In Timing Mode 1 the parallel transmit frame pulse PPFTo must be held in phase with the serial bus frame pulse
input (F0i). This is performed automatically by the MT90840 with an internal correction event, which moves the
PPFTo output. In normal TM1 operation the correction happens once on initialization, and does not happen again
as long as the C4/8 and PCKT clocks stay phase-locked.
If the clocks lose their phase lock, the MT90840 will assert an automatic correction, and set the TXPAA interrupt bit
high. The transmit parallel port data, the CTO control data and the TX frame pulse (PPFTo) will all jump phase due
to this correction, causing one errored TDM frame.
If a CPU write to the Transmit Path Connection Memory is occurring during the one PCKT clock cycle that clocks
the correction, there is a chance that the write data will go to address 0, rather than the intended address. To avoid
this it is necessary to keep clocks stable during TPCM programming in TM1 (including not using DIN while
programming). If there is some doubt about the quality of the clocks in a particular application, options include:
-1- Program the TPCM in TM2, or TM2 with internal clocks (INTCLK=1), where this clock correction does not occur.
-2- Monitor the TXPAA interrupt bit during TPCM programming, and check the intended address, and address 0, if
a TXPAA alarm occurs.
-4- Read/verify address 0 after a block of TPCM writes. If address 0 is corrupted, one of the writes occurred during
a clock correction.
Clock Quality and TM2 RPCM Access Integrity
In Timing Mode 2 the serial frame pulse F0o must be held in phase with the parallel port RX frame pulse (PPFRi).
This is performed automatically by the MT90840 with an internal correction event, which inverts the phase of the
SPCKo output. In normal operation the correction happens once on initialization, and does not happen again as
long as the C4/8 and PCKR clocks stay phase-locked.
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Zarlink Semiconductor Inc.