MT90840AP Zarlink, MT90840AP Datasheet - Page 15

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Timing Mode 1 (TM1) - Ring Master
Asynchronous Parallel Port With ST-BUS Clock Master
Timing Mode 1 is used where the main TDM clock reference resides on the serial port side of the system. (An
example is a node which is the clock master on a ring network.) Timing on the transmit parallel port is tightly tied to
the serial port. The receive parallel port timing is elastic; there is an elastic buffer in the Receive Path and the
Bypass Path. See Figure 5a for a connection example.
In TM1, the MT90840 receives the serial port frame pulse (F0i) and serial clock (C4/8R1 or C4/8R2). The MT90840
then generates the parallel port output frame pulse (PPFTo) synchronized to F0i. The transmit parallel port is fixed
in phase relative to the serial port. (A fixed offset of 3.8 µsec exists between F0i and PPFTo due to serial-to-parallel
conversion.) The transmit path does not provide an elastic buffer, and therefore the parallel port TX clock (PCKT)
must be tightly locked (in frequency) to the serial port C4/8 and F0i clocks. (Jitter less than +/- 100nsec.)
The receive parallel port timing may be of any phase relative to the serial and transmit-parallel ports in TM1. This
allows for flexible round-trip data delays in star or ring type networks. An elastic buffer on the receive parallel port
compensates for the difference in phase between PPFRi/PCKR and F0i/C4. The elastic buffer can also tolerate up
to 50 µsec +/- 25 µsec) of clock drift and jitter before the buffer re-syncs and Rx Path data is corrupted. (Data
corruption is flagged by the FSA interrupt source.) The Bypass Path data (PDi to PDo) also passes through the
elastic buffer in TM1.
In TM1, the MT90840's SPCKo clock output is not used.
TM1 Multiple-MT90840 Sub-Mode (PFDI)
For TM1 applications which require more serial channels than are provided by a single MT90840, it is possible to
operate multiple MT90840 in parallel. To do this, one MT90840 must control the F0i-to-PPFTo timing (normal TM1),
and the remaining MT90840s must synchronize to the first by using PPFTi as an input reference. The device
providing the reference will have the PFDI bit in the TIM Register set low (normal TM1). All other MT90840s will
have PFDI set high (forcing PPFT to be an input).
Figure 5b shows this mode using two MT90840s; additional MT90840s (with PFDI set high) may be added. This
sub-mode allows the serial ports of the multiple MT90840 to share one timing source, and the synchronized parallel
output ports to be connected together on one bus.
The TM1 Multiple-MT90840 sub-mode is not available for operation at 6.48 Mbyte/s.
8
8
RX Clock
8 kHz RX
Data RX
8 kHz TX
Data TX
TX Clock
Figure 5a - Timing Mode 1 Configuration
PCKR
PPFRi
PDi0-7
PCKT
PPFTo
PDo0-7
MT90840
CPU
Zarlink Semiconductor Inc.
C4/8R1
STo0-7
MT90840
STi0-7
F0i
15
8
8 STi/o 0-7
or 8.192 MHz
4.096
STi/o 0-7
8 kHz
PLL
Components
ST-BUS
Source
8 kHz
Data Sheet