MT90840AP Zarlink, MT90840AP Datasheet - Page 6

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Pin Description (continued)
45-52
84
42
55
56
57
58
59
60
61
62
65
Pin #
92-99
100
89
10
11
12
13
16
6
7
8
9
PPFTi/o
SPCKo
PDi7-0
PPFRi
Name
PCKR
PCKT
TRST
TMS
TDO
TCK
TDI
Parallel Port Framing, Transmit (Bidirectional). This signal delineates the start
of a new data frame at the PDo0-7 lines on the transmit parallel port. Normally an
output, when the PFDI bit in the TIM Register is set high PPFT becomes an input,
and is used to receive the frame reference from another MT90840. Used in all
timing modes except TM3.
Parallel Data Input Port 7 to 0 (Input). These eight inputs carry the parallel port
data bytes in the receive direction and operate at data rates up to 19.44 Mbyte/s.
Parallel Port Clock, Receive (Input). This is a 19.44, 16.384, or 6.48 MHz clock
input. It might typically be provided by a high speed framer. PCKR clocks in data
on the receive parallel port (PDi7-0 and PPFRi). In Timing Modes 2, 3, and 4,
PCKR clocks both the transmit and receive parallel ports.
Parallel Port Clock, Transmit (Input). This is a 19.44, 16.384, or 6.48 MHz clock
input. It might typically be provided by a high speed framer. In TM1 PCKT clocks
out the data on the transmit parallel port (PDo0-7, CTo0-3, and PPFTo). In TM2,
TM3, & TM4, this input is ignored.
Parallel Port Framing, Receive (Input). This 8 kHz frame pulse input determines
the start of a new frame at the PDi0-7 lines of the receive parallel port. It might
typically be connected to the frame pulse output of a high speed framer. In TM3,
PPFRi is the frame sync reference for both the transmit and receive parallel ports.
Test Data (Input). JTAG serial test instructions and data are shifted in on this pin
on rising TCK. This pin is pulled high internally when not driven.
Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing it
in the Test-Logic-Reset state. This pin is pulled high internally when not driven.
This pin should be pulsed low on power-up, or held low continuously, to ensure
that the MT90840 is in the normal functional state, and not the test state.
Test Clock (Input). Provides the clock to the JTAG test logic. This pin is pulled
high by an internal pull-up when not driven.
Test Mode Select (Input). JTAG signal that controls the state transitions of the
TAP controller, sampled on rising TCK. This pin is pulled high by an internal pull-
up when not driven.
Test Data (Output). JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG scan is not enabled.
Serial Port Clock (Output) In TM2 and TM3, this is a 4.096 MHz clock output
derived from the system 4.096 MHz reference. (As controlled by the C4/8R bit and
the INTCLK bit in the TIM Register.) This output is used to shift data in and out of
the serial port.
In TM1 and TM4, this output is automatically placed in high impedance.
For applications with the serial port running at 8.192 Mbps this output is not used,
and an 8.192 MHz clock source must be supplied at C4/8R1 or C4/8R2.
Zarlink Semiconductor Inc.
MT90840
6
Description
Data Sheet