MT90840AP Zarlink, MT90840AP Datasheet - Page 32

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

•
The signal at TMS selects the operational mode of the TAP Controller. The TMS signals are sampled on the rising
edge of TCK. This pin is pulled high internally when not driven.
•
Serial instructions and test-data are shifted in at this pin. Serial information is passed to the instruction register, the
boundary scan (test) register, or the bypass register, depending on the present mode of the TAP controller. TDI is
sampled on the rising edge of TCK. This pin is pulled high internally when not driven.
•
Serial data is shifted out on this pin. Depending on the present mode of the TAP controller, data will come from one
of: the instruction register, the boundary scan register or the bypass register. TDO is clocked out on the falling edge
of TCK. When no data is being shifted, the TDO driver is set to a high-impedance state.
•
Asynchronously initializes the TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled high
internally when not driven.
One additional pin influences the boundary scan test operation:
•
This pin is an IEEE 1149 compliance-enable pin, and must be connected to Vss for proper boundary scan operation
(and normal chip operation).
Boundary-Scan Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90840 uses public instructions listed in Table 3 - “Instruction
Register”. The MT90840 JTAG Interface contains a two bit instruction register. Instructions are serially loaded into
the Instruction Register from the TDI pin when the TAP Controller is in its Shift-IR state. Subsequently, the
instructions are decoded to achieve two basic functions: to select the test data register that may operate while the
instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO
during data register scanning.
[00]
[01]
[10]
[11]
I[0:1] Instruction
Test Mode Select Input (TMS)
The Test Data Input (TDI)
The Test Data Output (TDO)
TRST:(Test reset input)
IC: (Manufacturing test pin)
EXTEST
SAMPLE/PR
ELOAD
BYPASS
Boundary-Scan
Register selected,
Test enabled
Boundary-Scan
Register selected,
Test disabled
Bypass Register
selected,
Test disabled
Table 3 - Boundary-Scan Instruction Register
This instruction is specifically provided to allow board-level interconnect
testing of opens, bridging errors etc.
When the EXTEST instruction is executed, the MT90840 core logic is
isolated from the I/O pins, and the state of the I/O pins is determined by
the boundary-scan register. I/O data for this instruction is pre-loaded into
the boundary-scan register with the SAMPLE/PRELOAD instruction.
Two functions can be performed by the use of this instruction. It allows a
SAMPLE (‘snapshot’) of the normal operation of the MT90840 to be
taken for examination. And, prior to the selection of another test
operation, a PRELOAD can place data values into the latched parallel
outputs of the Boundary-Scan cells. During the execution of the
instruction, the on-chip logic operation is not hampered in any way.
This instruction is used to BYPASS the MT90840 while performing
boundary-scan testing on other devices with scan registers in the same
serial register chain. The MT90840 is allowed to function normally. This
instruction is automatically loaded upon TRST, as specified in
IEEE1149.1
Zarlink Semiconductor Inc.
MT90840
32
Description
Data Sheet