MT90840AP Zarlink, MT90840AP Datasheet - Page 14

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

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The parallel port of the MT90840 is flexible enough to interface to a variety of applications. It can be connected to a
framer to access a serial transport backbone running at up to 155 Mbps. It can be connected to a backplane-type
parallel bus. It can share a parallel bus with other devices, using the control outputs (CTo0-3) and the per-channel
tristate function to share access to the bus.
Parallel Port Clock Signals and Framing
The MT90840's PPFRi (Parallel Port Frame pulse Receive input) and PPFTi/o (Parallel Port Frame pulse Transmit
i/o) signals synchronize the MT90840 to the high speed data frame. Receive data is clocked in at the Parallel Data
inputs (PDi0-7) by the Parallel port Receive ClocK (PCKR), as framed by Receive Parallel Port Frame input
(PPFRi). In TM2, TM3 and TM4, PCKR also clocks the Parallel Data outputs (PDo0-7), with the framing in TM2 and
TM4 indicated by the PPFTo output. In TM1, the Parallel Data outputs are clocked out by PCKT, with the framing
indicated by PPFTo. Alternatively, the Transmit framing can be controlled by the PPFTi input if the PFDI bit in the
TIM register has been set high, to enable multiple MT90840s to operate in parallel in TM1.
Should the input framing at PPFRi cease while the PCKR clock continues to run, the MT90840 will continue to
function as if the frame pulse was asserted after the normal number of clock cycles (free run). If PPFRi re-
commences, the MT90840 will immediately sync to PPFRi, but any change in the framing interval will temporarily
disrupt the TDM data streams, and trigger the PPCE interrupt bit. PPCE will be triggered by PPFRi moving from the
expected time, but PPCE will not be triggered by a missing PPFRi. If the PPFRi input is held asserted, the parallel
I/O will “lock up” and operation will be disrupted (including CPU access to the TPCM).
The PPFTi framing in TM1 with PFDI=1 operates similarly, using PCKT, but the PPCE interrupt does not monitor
PPFTi. Instead, the TXPAA bit indicates that the PPFTi input is out of phase with F0i.
Output Driver Enable Control Capability
The MT90840 provides a bit (ODE) in the IMS Register that places all data outputs of the device (parallel and
serial) in a high impedance state. The ODE bit (Output Drive Enable) is automatically set low by the reset input
pulse applied to the device during system power up. When low, the ODE bit disables all TDM outputs of the
MT90840 while Connection Memory initialization is performed by the CPU. This function is useful to avoid data
collision when the MT90840 is sharing a transmit parallel bus with other devices. When ODE is set high, individual
parallel and serial port time slots are controlled by the OE bits in TPCM High and RPCM High.
Timing and Switching Control
The MT90840 supports four major timing/switching modes:
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The TM1-0 bits in the TIM Register are used to select the timing modes. The PFDI and SFDI bits in the same
register can be used to enable parallel-device sub-modes of TM1 and TM2 respectively. In all MT90840 timing
modes, the throughput delay when performing time interchange functions of grouped channel data is constant,
maintaining the frame integrity of the input and output data.
the use of PPFT (normally an output) as an input in TM1, if the application requires multiple MT90840
devices to operate in parallel (see PFDI bit in the TIM register).
TM1/Ring Master: PDo timing slaved to STi/o timing, Receive Path has elastic buffer enabled;
TM2/Ring Slave: STi/o timing slaved to PDi timing, fixed delay in Receive Path;
TM3/Bus Slave: PDo and PDi tied together, STi/o timing slaved to parallel bus timing;
TM4/Parallel Switching: 2430 (or 2048) channel switching from PDi to PDo.
Zarlink Semiconductor Inc.
MT90840
14
Data Sheet