NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 119

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NUC130LE3CN

Manufacturer Part Number
NUC130LE3CN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130LE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130LE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130LE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
Interrupt Control State Register (ICSR)
Register
ICSR
Bits
[31]
[30:29]
[28]
[27]
NMIPENDSE
ISRPREEMP
31
23
15
T
T
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Reserved
Offset
SCS_BA+0xD04
ISRPENDING
Descriptions
NMIPENDSET
Reserved
PENDSVSET
PENDSVCLR
VECTPENDING[3:0]
30
22
14
6
Reserved
R/W
R/W
NMI set-pending bit
Write:
0 = no effect
1 = changes NMI exception state to pending.
Read:
0 = NMI exception is not pending
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally the processor enters the NMI
exception handler as soon as it detects a write of 1 to this bit. Entering the handler then
clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1
only if the NMI signal is reasserted while the processor is executing that handler.
Reserved
PendSV set-pending bit.
Write:
0 = no effect
1 = changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
PendSV clear-pending bit.
Write:
0 = no effect
29
21
13
5
Description
Interrupt Control and State Register
PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR
28
20
12
4
- 119 -
Reserved
VECTACTIVE[5:0]
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
Reserved
VECTPENDING[5:4]
25
17
9
1
Revision V2.01
Reset Value
0x0000_0000
Reserved
24
16
8
0

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