NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 202

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.6.4.5
5.6.4.6
condition during this action when bus error occurs.
The data baud rate of I
not important when I
with any clock frequency from master I
The data baud rate of I
If system clock = 16 MHz, the I2CLK [7:0] = 40 (28H), so data baud rate of I
+1)) = 97.5 Kbits/sec.
There is a 14-bit time-out counter which can be used to deal with the I
out counter is enabled, the counter starts up counting until it overflows (TIF=1) and generates I
interrupt to CPU or stops counting by clearing ENTI to 0. When time-out counter is enabled,
setting flag SI to high will reset counter and re-start up counting after SI is cleared. If I
hangs up, it causes the I2CSTATUS and flag SI are not updated for a period, the 14-bit time-out
counter may overflow and acknowledge CPU the I
bit time-out counter. User may write 1 to clear TIF to zero.
I
The I
2
C Clock Baud Rate Bits (I2CLK)
NuMicro™ NUC130/NUC140 Technical Reference Manual
2
C Time-out Counter Register (I2CTOC)
2
C is in a slave mode. In the slave modes, I
2
2
Figure 5-26: I
C setting is Data Baud Rate of I
C is determines by I2CLK [7:0] register when I
2
C Time-out Count Block Diagram
2
C device.
- 202 -
2
C interrupt. Refer to the Figure 5-26 for the 14-
2
C = (system clock) / (4x (I2CLK [7:0] +1)).
Publication Release Date: June 14, 2011
2
C will automatically synchronize
2
2
C is in a master mode. It is
C bus hang-up. If the time-
2
C = 16 MHz/ (4x (40
Revision V2.01
2
C bus
2
C