NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 323

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.11 Watchdog Timer (WDT)
5.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wake-up chip from power down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals. Table 5-7 show the
watchdog timeout interval selection and Figure 5-64 shows the timing of watchdog interrupt signal
and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is
set, in the meanwhile, a specified delay time (1024 * T
set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid chip
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset chip. This reset will last 63 WDT clocks (T
then chip restarts executing program from reset vector (0x0000_0000). WTRF will not be cleared
by Watchdog reset. User may poll WTRF by software to recognize the reset source. WDT also
provides wake-up function. When chip is powered down and the Watchdog Timer Wake-up
Function Enable bit (WDTR[4]) is set, if the WDT counter reaches the specific time interval
defined by WTIS (WDTCR [10:8]) , the chip is waken up from power down state. First example, if
WTIS is set as 000, the specific time interval for chip to wake up from power down state is 2
T
2
(WDTCR [10:8]) is set as 111, the specific time interval for chip to wake up from power down
state is 2
state. After 2
(WDTCR [1]) is set to 1, after chip is waken up, software should clear the Watchdog Timer
counter by setting WTR(WDTCR [0]) to 1 as soon as possible. Otherwise, if the Watchdog Timer
counter is not cleared by setting WTR (WDTCR [0]) to 1 before time starting from waking up to
software clearing Watchdog Timer counter is over 1024 * T
Timer.
4
WDT
* T
. When power down command is set by software, then, chip enters power down state. After
WDT
NuMicro™ NUC130/NUC140 Technical Reference Manual
18
time is elapsed, chip is waken up from power down state. Second example, if WTIS
* T
WTIS
18
000
001
010
011
100
101
WDT
* T
WDT
. If power down command is set by software, then, chip enters power down
Timeout Interval
time is elapsed, chip is waken up from power down state. Notice if WTRE
2
2
2
Selection
2
2
2
10
12
14
4
6
8
T
* T
* T
* T
* T
* T
* T
TIS
WDT
WDT
WDT
WDT
WDT
WDT
Interrupt Period
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
- 323 -
T
INT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WTR Timeout startingInterval
Publication Release Date: June 14, 2011
MIN. T
) follows the time-out event. User must
102.4 ms ~ 204.8 ms
(WDT_CLK=10 kHz)
1.6384 s ~ 1.7408 s
409.6 ms ~ 512 ms
6.4 ms ~ 108.8 ms
25.6 ms ~ 128 ms
1.6 ms ~ 104 ms
WDT
WTR
, the chip is reset by Watchdog
~ Max. T
WTR
Revision V2.01
RST
4
*
)