NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 409

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Message Interface Register Sets
There are two sets of Interface Registers, which are used to control the CPU access to the
Message RAM. The Interface Registers avoid conflict between the CPU accesses to the
Message RAM and CAN message reception and transmission by buffering the data to be
transferred. A complete Message Object or parts of the Message Object may be transferred
between the Message RAM and the IFn Message Buffer registers in one single transfer.
The function of the two interface register sets is identical except for the Basic test mode. They
can be used the way one set of registers is used for data transfer to the Message RAM while the
other set of registers is used for the data transfer from the Message RAM, allowing both
processes to be interrupted by each other. Table 5-19 (IF1 and IF2 Message Interface Register
Set) provides an overview of the two Interface Register sets.
Each set of Interface Registers consists of Message Buffer Registers controlled by their own
Command Registers. The Command Mask Register specifies the direction of the data transfer
and which parts of a Message Object will be transferred. The Command Request Register is
used to select a Message Object in the Message RAM as target or source for the transfer and to
start the action specified in the Command Mask Register.
CAN0_BA+0x20
CAN0_BA+0x24
CAN0_BA+0x28
CAN0_BA+0x2C
CAN0_BA+0x30
CAN0_BA+0x34
CAN0_BA+0x38
CAN0_BA+0x3C
CAN0_BA+0x40
CAN0_BA+0x44
CAN0_BA+0x48
Address
NuMicro™ NUC130/NUC140 Technical Reference Manual
IF1 Command Request
IF1 Command Mask
IF1 Mask 1
IF1 Mask 2
IF1 Arbitration 1
IF1 Arbitration 2
IF1 Message Control
IF1 Data A 1
IF1 Data A 2
IF1 Data B 1
IF1 Data B 2
Table 5-19 IF1 and IF2 Message Interface Register
IF1 Register Set
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CAN0_BA+0x80
CAN0_BA+0x84
CAN0_BA+0x88
CAN0_BA+0x8C
CAN0_BA+0x90
CAN0_BA+0x94
CAN0_BA+0x98
CAN0_BA+0x9C
CAN0_BA+0xA0
CAN0_BA+0xA4
CAN0_BA+0xA8
Address
Publication Release Date: June 14, 2011
IF2 Command Request
IF2 Command Mask
IF2 Mask 1
IF2 Mask 2
IF2 Arbitration 1
IF2 Arbitration 2
IF2 Message Control
IF2 Data A 1
IF2 Data A 2
IF2 Data B 1
IF2 Data B 2
IF2 Register Set
Revision V2.01