NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 15

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• I
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• PS/2 Device Controller
• CAN 2.0
• EBI (External bus interface) support (100-pin and 64-pin Package Only)
• ADC
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NuMicro™ NUC130/NUC140 Technical Reference Manual
Up to two sets of I
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allow versatile rate control
Support multiple address recognition (four slave address with mask option)
Interface with external audio CODEC
Operate as either master or slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Mono and stereo audio data supported
I
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Support two DMA requests, one for transmit and one for receive
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
32 Message Objects
Each Message Object has its won identifier mask
Programmable FIFO mode (concatenation of Message Object)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Support power down wake-up function
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Support 8-/16-bit data width
Support byte write in 16-bit data width mode
12-bit SAR ADC with 700K SPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion start by software programming or external input
2
S and MSB justified data format supported
2
C device
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Publication Release Date: June 14, 2011
Revision V2.01