PEB20320H-V34RF Infineon Technologies, PEB20320H-V34RF Datasheet - Page 126

• Manufacturer Part Number: PEB20320H-V34RF
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34RF

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, ISDN, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34RF; PEB20320H-V34RFIN

User’s Manual
2.5
In MUNICH32 a Test Access Port (TAP) controller is implemented. The essential part of
the TAP is a finite state machine (16 states) controlling the different operational modes
of the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE Std. 1149.1. Figure 73 gives an overview.
Figure 73
Block Diagram of Test Access Port and Boundary Scan
Test handling is performed via the pins JTEST0 (TCK), JTEST1 (TMS), JTEST2 (TDI)
and JTEST3 (TDO). Test data at JTEST2 (TDI) are loaded with a 4-MHz clock signal
connected to JTEST0 (TCK). ‘1’ or ‘0’ on JTEST1 (TMS) causes a transition from one
controller state to an other; constant ‘1’ on JTEST1 (TMS) leads to normal operation of
the chip.
If no boundary scan testing is planned JTEST1 (TMS) and JTEST2 (TDI) do not need to
be connected since pull-up transistors ensure high input levels in this case. Nevertheless
it would be a good practice to put the unused inputs to defined levels. In this case, if the
JTAG is not used:
JTEST1 = JTEST0 = ‘1’.
After switching on the device (
the TAP controller into test logic reset state.
JTEST0 (TCK)
JTEST1 (TMS)
JTEST2 (TDI)
JTEST3 (TDO)
Boundary Scan Unit
CLOCK
Test
Control
Data IN
Enable
Data OUT
Test Access Port
Generation
Clock
V
-Finite State Machine
-Instruction Register (3 bits)
-Test Signal Generator
DD
CLOCK
= 0 to 5 V) a power-on reset is generated which forces
TAP Controller
126
Power ON
Reset
Reset
BS Data IN
Control Bus
ID Data OUT
SS Data OUT
6
Functional Description
PEB 20320
01.2000
1
2
n
ITB03509
Pins