PEB20320H-V34RF Infineon Technologies, PEB20320H-V34RF Datasheet - Page 32

• Manufacturer Part Number: PEB20320H-V34RF
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34RF

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, ISDN, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34RF; PEB20320H-V34RFIN

User’s Manual
2
2.1
The serial interface of MUNICH32 includes a data receive (RDATA) and a data transmit
line (TDATA) as well as the accompanying control signals (RCLK = Receive Clock,
RSP = Receive Synchronization Pulse, TCLK = Transmit Clock, TSP = Transmit
Synchronization Pulse). The timings of the receive and transmit PCM highway are
independent of each other, i.e. the frame positions and clock phases are not correlated.
Data is transmitted and received either at a rate of 2.048 Mbit/s for the CEPT 32-Channel
European PCM format (Figure 14) or 1.544 Mbit/s or 1.536 Mbit/s for the
T1/DS1 24-Channel American PCM format (Figure 12 and Figure 13). MUNICH32 may
also be connected to a 4.096-Mbit/s PCM system (Figure 15), where it handles either
the even- or odd-numbered time slots, so all 64 time slots can be covered by connecting
two MUNICH32s to the PCM highway.
The actual bit rate of a time slot can be varied from 64 Kbit/s down to 8 Kbit/s for the
receive and transmit direction. A fill mask code specified in the time slot assignment
determines the bit rate and which bits of a time slot should be ignored. Any of these
time slots can be combined to a data channel allowing transmission rates from 8 Kbit/s
up to 2.048 Mbit/s.
The frame alignment is established by the transmit and receive synchronization pulse
(TSP, RSP), respectively. The sampled rising edge of TSP identifies the current bit on
the serial line (TDATA) as the last bit of a PCM frame. The sampled rising edge of RSP
indicates that the current bit on the serial line (RDATA) is the first bit of a PCM frame.
The F-bit for the 1.544 MHz T1/DS1 24-channel PCM format is ignored in receive
direction, the corresponding bit is tristate in transmit direction. It is therefore assumed
that this channel is handled by a different device.
For test purposes four different test loops can be switched. In a complete loop all logical
channels are mirrored either from serial data output to input (internal loop) or vice versa
(external loop).
In a channelwise loop one single logical channel is logically mirrored either from serial
data output to input (internal loop) or vice versa (external loop).
A detailed description of the different loops is found in Chapter 4.2.1 and Chapter 5.1.
Functional Description
Serial Interface
32
Functional Description
PEB 20320
01.2000