PEB20320H-V34RF Infineon Technologies, PEB20320H-V34RF Datasheet - Page 169

• Manufacturer Part Number: PEB20320H-V34RF
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34RF

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, ISDN, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34RF; PEB20320H-V34RFIN

HI:
NO:
Receive Descriptor
FE:
C:
User’s Manual
00000000.00001000.00000000.00000
11000000.00000001.Status.00000000
receive data pointer
next receive descriptor pointer
The HOLD condition is also discarded upon detection of a receive jump, fast
receive abort or receive initialization command. The MUNICH32 then
branches to the receive descriptor determined by FRDA even though the
HOLD bit in the current receive descriptor may still be ‘1’.
Host initiated interrupt; if the HI bit is set, MUNICH32 generates an interrupt
with set HI bit after receiving all data bytes.
This byte number defines the size of the receive data section allocated by the
host. Because MUNICH32 always writes long words the number of bytes
(data section size) must be a multiple of 4 and greater or equal to 4. The
maximum data section size is 8188 bytes.
After reception of an HDLC frame with a data byte number not divisible by 4
MUNICH32 first transfers the greatest entire ([number of data bytes/4]) in long
words. Then the remainder of the data bytes is transferred in another long
word, where the non-significant bytes are filled with random values. They
should not be interpreted.
For example a HDLC frame with one data byte is received:
The data bytes are stored into the receive data section according to the Little
Endian convention (Intel mode) or Big Endian convention (Motorola mode).
Frame End: The frame end bit is ‘1’ only in HDLC, TMB, TMR mode and
indicates that a receive frame has ended in this receive descriptor. For TMA,
V.110/X.30 the bit is always ‘0’.
FE = 0 in HDLC, TME, TMR mode means that frame continues in the next
receive descriptor or that it filled the current receive data section exactly (BNO
= NO). In this case the next receive descriptor will have FE = 1, C = 1, BNO
= 0 and no data bytes are stored in the corresponding data section.
This bit is set by MUNICH32 if
• it completes filling the data section normally (BNO = NO)
• it was aborted by a fast receive abort channel command
status = 00
• For V.110/X.30, TMA the device puts the next data into the next receive
detected. Afterwards the next received frame is transferred into the next
receive descriptor. Interrupts are also generated again.
descriptor. Interrupts are also generated again.
169
Receive Data Section
XX.XX.XX.data
Detailed Register Description
status = 02
PEB 20320
FE = 0,
01.2000