AT90PWM216 Atmel Corporation, AT90PWM216 Datasheet - Page 35

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AT90PWM216

Manufacturer Part Number
AT90PWM216
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT90PWM216

Flash (kbytes)
16 Kbytes
Pin Count
24
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
19
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
1
Pwm Channels
7
32khz Rtc
No
Calibrated Rc Oscillator
Yes
7.6.2
7710F–AVR–09/11
PLL Control and Status Register – PLLCSR
Figure 7-3.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM216/316 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
Bit
$29 ($29)
Read/Write
Initial Value
PLL
XTAL1
XTAL2
for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
RC OSCILLATOR
OSCCAL
8 MHz
PCK Clocking System AT90PWM216/316
OSCILLATORS
R
7
0
R
6
0
CKSEL3..0
R
5
0
DIVIDE
BY 8
R
4
0
PLLE
PLL
64x
R
3
0
Detector
Lock
DIVIDE
DIVIDE
PLLF
PLLF
BY 2
BY 4
R/W
AT90PWM216/316
2
0
PLLE
R/W
0/1
1
PLOCK
CLK
PLOCK
R
0
0
CK
PLL
SOURCE
PLLCSR
35

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